SU1243159A2 - Device for compression of digital signals - Google Patents

Abstract

The invention is additional to the device of. main auth. No. 1146831. The distortion of the television signal is reduced by reducing the distortion of oblique contours. The input signal is received. on the block 1 of the installation of the reference level and on the block 2 of the analog-digital conversion (L to 4 oo el N0

Description

to disperse. From its release, the seven-way parallel code arrives at the summing memory register (RP) 7. directly, via delay element 6 - per line and at RP 10. The code from summing RP 7 is rewritten sequentially and RP 8 and 9. The information transmitted to the communication channel through switch 4 depends on the comparison of the four most significant bits of the corresponding samples rows in blocks of comparison (BS) P-14. Elements j and lines are transmitted by even counts with information about the true values of the bits of the source code. The elements (j + O-th row-are transmitted through the readout information, depending on the comparison results in BS 12, to which (1-1) st and (1 + 1) -th readings of the j-th row are sent, in BS 13 On which (1-1) -th counting are given

The invention relates to telecommunications, in particular to television image transmission systems, and can also be used in telegraphy, namely in devices with code conversion within the transmitter, and is an improvement to the device according to the author. St. No. 1146831.

The purpose of the invention is to reduce the distortion of the television signal by reducing the distortion of the inclined contours.

Fig. 1 shows a structural electrical circuit for compressing digital television signals; Fig. 2 is a block diagram of an analog-to-digital conversion unit; FIG. 3 is a block diagram of the control unit; figure 4 is a block diagram of the switch; figure 5 - structural diagram of the delay element; Fig. 6 is a block diagram of a summing memory register; Fig. 7 is a block diagram of a second comparing unit; FIG. 3 shows the structural diagram of a first comparison unit, a unit for selecting transmitted signals, a memory management unit; in fig. 9 - block diagram of the block

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j-lines and n-and counting (d + 1) -th line, in BS 14, to which (1-1) -th and i-th samples of the j -th line are sent, to BS 26, to which ( 1-) -th countdown of the Jth row and (1-1) -th countdown (5 + 2) -th row. Comparison results are sent to the appropriate blocks, 20–23 write resolutions. Additional information about the nature of the recovery of the missing elements is generated by pilot block 24. The nature of the additional information O or 1 depends on the result of the comparison in BS 14. The delay elements 25 (two lines) and BS 26 that are entered allow using the information from the previous work cycle about the four leading bits of the (i-1) -th reference (t + 2) and lines. Block 3 control, aleni ensures synchronous operation of the blocks of the device. 24 Il.

memory; Fig. 10 is a block diagram of a lower order memory block; Fig. 11 is a block diagram of the first recording resolution block; Fig. 12 is a block diagram of a second recording resolution block; in fig. 13 is a block diagram of a third recording resolution block; Fig. 14 is a block diagram of a fourth recording resolution block; in fig. 1 5 - block diagram of the pilot signal; FIG. 16 is a block diagram of an additional element of the holder; in fig. 17 - characteristic distortion of oblique contours;

Fig. 18 shows timing charts of operation of the control unit; Fig. 19 shows timing charts of a memory register; on Fig - time diagrams of the first block

permission to record; Figure 21 shows the time diagrams of the second recording resolution block; Figure 22 shows the timing diagrams of the third recording resolution block; 23 shows timing charts of the operation of the pilot block; on Fig - time diagrams of the fourth block of permits. write.

A device for compressing digital. TV signals (Fig. 1) contains a reference level setting unit 1, an analog-to-digital conversion unit 2, a control unit 3, a switch 4, a synchronization code generator 5, a delay element 6, summing the memory register 7, first memory register 8, the second memory register 9, third memory register 10, first compare block 11, second compare block 12, third compare block 13, fourth compare block 14, select block 15, transmittable characters, encoder 16, memory control block 17, block 18 memories, block 19 memories of lower order bits, the first block 20 is resolved neither a recording, a second recording resolution block 21, a third recording resolution block 22, a fourth recording resolution block 23, a pilot signal block 24, an additional delay element 25, an additional comparison block 26,

The analog-to-digital conversion unit (Fig. 2) comprises an analog-to-digital converter 27, a reference voltage generator 28, a clock generator 29, a driver 3 short pulses,

The control unit of FIG. 3 contains a clock frequency divider 31, a line frequency divider 32, a digital delay line 33, an AND-NE element 34.

The switch (Fig. 4) contains a block 35 for selecting the first bit of the channel code, OR-NOT elements 36 and 37, an OR 38 element, a second block selecting block 39, a channel code selecting block 40, a fourth code block 41 code bit. channel, block 42 memory channel code.

The delay element (Fig. 5) contains an address generation unit 43, four-bit counters 44-1.44-2 44-3, a memory element 45, a memory element 46-7 of one bit.

The summing memory register (Fig. 6) contains the elements OR-NOT 47 and 48, the recording permission block 49, the elements OR-NOT 50-1.50-2, the elements 51 of the memory, the element 52-1 of the memory of one bit.

The second comparison unit (Fig. 7) contains a block 53 for determining prohibited changes, block 54 for determining changes, block 55 for selecting allowed changes.

The memory management unit (FIG. 3) contains prohibition blocks 56-1 ... 56-8., Installation blocks 57-1 ... 57-4

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bits, blocks 58-1 ... 58-6, the choice of installation of young bits.

The memory block (FIG. 9) contains memory elements 59-1 ... 59-7 of memory of 5 code series, memory elements OR 60-1.60-2, memory elements 61-1 and 61-2, digital differentiating chains 62-1 ... 62-4, elements OR 63-1 and 63-2.

The first recording resolution block 10 (Fig. 11) contains elements OR 64-1 and 64-2, elements 65-1 and 65-2 of memory, elements 66-1.66-2 and 66-3 matches, elements NOT 67- 1 and 67-2.

The second recording resolution block 15 (Fig. 121 contains AND elements 68,

memory element 69, resolution block 70.

The third recording resolution block (Fig. 13) contains elements 71 and 72 20 of match, elements 73 and 74 of memory, NOT 75, elements OR-NOT 76 and 77..

The fourth recording resolution block 25 (FIG. 14) contains elements 78-80 of coincidence, elements HE 81 and 82.

The pilot block (Fig. 15) contains an OR / OR-NO 83 element, memory elements 84 and 85, elements 86 2Q and 87 matches, element NOT 88, element OR 89, elements OR-NOT 90 and 91, element OR 92

The second delay element (Fig. 16) contains the address forming block 93, the memory elements 94 and 95, the HE element 96.

A device for compressing digital television signals works as follows.

The input signal is fed to the analog input of the analog-to-digital converter 27, which is also supplied with voltage from the output of the reference voltage generator 28 and to short pulses from the output of the short-pulse driver 30.

The reference level setting unit 1 is a serial connection of an amplitude selector and a multivibrator. The amplitude selector is made according to a typical scheme, its input receives an analogue television signal, and the output has a mixture of sync pulses from the lowercase and frame ones, and the multivibrator produces a combination of synchro pulses short pulses that serve to set the corresponding blocks and circuits to their initial state.

40

five

The control unit 3 contains horizontal dividers 32 and clock frequencies 31. Dividers are assembled on 13 triggers in counting mode. The R-input divide - § 31 clock frequency receives the setting signal from the output of the reference level setting block 1, the same signal arrives at the C-input of the divider 32 horizontal frequency. Output signals 10 are removed from the direct and inverse outputs of the flip-flops. At the same time, the clock frequency is fed to the input of the digital delay line 33, which is a series 5 connection of the OR elements with the taps. The set-up output is obtained when the sixth tap of the digital delay line and the inverse output of the divider 20 31 clock frequency coincide on the AND-HE element 34. A switch consists of units for selecting channel code bits 35,39,40,41 and a channel code memory block 42. Common entrance is two-. input elements OR 35, 39, 40, 41 correspond to the second control input of switching unit 4, the common input of three input elements OR 35, 39, 40, 41 correspond to the first control input of switching unit 4, with a second control input OR the bits from the second input of the switching unit 4 are combined with the signal at the first control input of the union. are located in blocks 35, 39, 40, 4 of the signal from the fourth input of the switching unit 4. In addition, in the blocks 35, 39, the signals of the first input of the switching unit 4 are additionally combined, and in the circuits 40 and 41, the signals from the third 40 input of the switching unit 4 are combined. The channel code code 42 block is a line of five D triggers, on the inputs of which the outputs of the code bit selection blocks of the channels 35, 45 39, 40, 41 are entered, to the fifth trigger signal from the fifth block of the switching unit , and the synchro-signal of the synchronous input of the switching unit 4 is turned on at the C-inputs. The outputs of the flip-flops of the block 42 of the memory of the channel code 50 are the outputs of the switching unit 4 and the entire device. The synchronization code shaper 5 is a multiplexer, at the input of which a specific code is set and written down to the communication channel when the installation pulses pass from the unit 1 output (reference level. The first delay element 6 is assembled on the memory elements with a volume of 1024 bits, one for each bit and an address generation unit 43. The address generation unit 43 is a ten-bit counter, a serial connection of three four-bit counters, the initial setting of which is is outputted by a pulse from the setup input of the delay element 6, and starting from the clock input. The counter outputs are connected to the corresponding address inputs of the memory elements. The transfer from the write mode to the read mode is performed by a signal from the control input which is connected to the memory control input. The dry register 7 (Fig. 6) is two elements OR NOT 47 and 48, recording resolution block 49, and memory element 51. The common input of the elements OR NOT is signaled from the first control input of the summing register 7 memory ti The other two inputs are fed to the second and third control inputs respectively. The recording permission block 49 is the seven elements OR NOT. The common inputs of the elements are supplied with control signals from the output of the OR-NOT 47 and 48 elements, and to the other information inputs from the corresponding outputs of the analog-to-digital conversion unit 2 and the delay element 6, the outputs of the circuit 49 allow no recording to the element 51 memory, which is a line of T) -triggers 52-1, one for each bit, the input is the D-input of the flip-flops, on the C-input of which the clock signal is supplied from the sync input. The first output of the memory register 7 corresponds to the direct outputs of the trigger elements of the memory element 51, and the second output to the inverse outputs of the D-flip-flops. The first 8 and second 9 memory registers are the trigger lines, one for each bit. Information is recorded on the D input when the sync input (C input of the triggers) is received by the sync signals. The forward outputs of the triggers are the first outputs of the registers, the inverse outputs are the second outputs of the registers 8 and 9 of the memory. The third memory register 10 is a line of four D-flip-flops for the four most significant bits and an OR element whose output is connected to the C input of the flip-flops, and the inputs of the first and second control inputs and the sync input. The output of the third memory register 10 is the inverse outputs of the flip-flops. The first comparison unit 1 (Fig. 8 is the three elements P1SOLUTE THROUGH OR OR for the three least significant bits, one inputs of which are supplied with the corresponding least significant bits from the first output of the second register 9 of the memory. The outputs of the EXCLUSIVE YNN are outputs The second, fourth, and fifth units of comparison are made according to the same scheme (Fig. 7) and consist of a change detection unit 54, a definition of prohibited changes 53, and a block of allowed changes selection 55. The change definition unit 54 is four

D elements OR EXCLUSIVE OR, which make a comparison of the four higher-order bits arriving at the first and second inputs of block 12. The block 53 for determining prohibited changes also consists of the elements EXCLUSIVE CEE OR ,. the corresponding outputs of which are combined by OR, the block for selecting allowed changes consists of the elements OR and OR NONE, which, taking into account the prohibitions from block 53, transmit information about the presence of changes in at least one of the four senior classes obtained in block 54. The second the output of the comparison blocks 12 and 14 is the inverse of the first output. The third comparison block 13 is the combination of OR for the four elements EXCLUSIVE OR, with four high-order bits from the first and second inputs being input to them. The transmitted symbol selection unit 15 is two prohibition blocks (FIG. B). The presence of a change in the character in a higher bit of block 11 prohibits the passage of information about a change in the character in a lower bit in block 15. The outputs of block 15 are the inverse of one relative to another. 11 If the transmitter 16 is the actual encoder and the OR elements, combining the output and the second input

the encoder 16. Their output is the output 1 of the typhrarator 16. The memory control block 17 (FIG. 81 is eight prohibition blocks 56-1 ... 56-8, four blocks 57-1 ... 57-4 of the lower settings). bits, six blocks 58-1 .. .58-6 of the installation of the lower bits. Blocks 57-1 and 57-2 of the low bits installation simultaneously set three lower bits of the memory block 18 when recording true state information in it for the four higher bits, for this purpose, their outputs are fed to the R and S inputs of the trigger elements of the memory of the three lower bits of the memory block 18, respectively. Blocks 57-3 and 57-4 low-order settings install two low-order bits of memory block 18, for which their outputs are also fed to the R and S inputs of memory element trigger elements of block 18. For installation of low-order bits only blocks 56-1.. 56-8 of the prohibition, for one input of which differentiated pulses are fed from the direct outputs of high-order trigger bits of the memory block 18, and for the second forbidding entrances - from

inverse outputs of block triggers

I

18 memory. To install the younger ones

bits in accordance with the received processing algorithm for signals from block 15 for selecting the transmitted symbol slu.-at blocks 58-1 ... 58-6 for setting the low-order bits, the combined outputs of which correspond to the first input of block 17 for memory management, and The second inputs are supplied with information from the direct and inverse outputs of the low-order memory elements of the memory block 18. The outputs of blocks 58-1 ... 58-6 of the installation of the low-order bits are also fed to

R and S inputs of the trigger elements I

memory block 18 memory. The memory unit 18 is seven, one for each bit, memory elements 59-1 .. .59 (Fig. 9). The four elements 59-1 ... 59-4 of the memory for the higher-order bits are assembled according to the same g scheme AND represent the OR element (in Fig.9, one of the four elements is revealed), the memory element and digital differentiating circuits. The signal from the setup input is fed to

The ft input of the triggers on which the memory elements are collected, the C input signal is supplied from the sync input, the D input is given to the signal from the output of the OR element, to the input of which signals from the second and fourth inputs of the memory block 18 are input. The outputs of the memory element are connected to diffracting differentiating chains, made according to the Typical circuit. The memory elements for the lower bits 59–5., 59–7 are characterized by the addition of 1–1 OR elements for the third bit, which expand the possibility of setting the triggers of the memory elements to the required state via the R and S inputs. Elements 59-6 and 59-7 of memory have no digital differentiating chains. The input signal for them is the third input of the memory block 18, the first output of the memory block 8 is formed by the direct outputs of the trigger elements 59-5.59-6, G 59-7 of the memory. The second output of memory block 18 is formed by the outputs of digital differentiating chains of elements 59-1., -. 59-5 memory direct and inverse inputs of the trigger elements 59-5. 59-7 memory. The lower memory bit unit 19 is a ruler (FIG. 10) of three flip-flops, the D-inputs of which are supplied with the lowest code bits from the second output of the first 2P module. The first recording resolution block 20 is (FIG. 11) two AND 64-1, 64-2, two memory elements 65-1 and 65-2, three blocks 66-1.66-2.66-3 matching and the element NOT 67-1, Signals from the sync input, the first and second control inputs are sent to both elements AND, the signal from the third control input is still sent to element 64-2. The outputs of the And 64-1 and 64-2 elements are connected to the S-inputs of the trigger elements 65-1 and 65-2 gs, on the R-inputs of which the signal is fed from the installation input. The first matching block skips the four high bits to the output from the output of the first recording resolution block 20 when they match the signal at the first control input, the second matching block skips the third bit at the output resolution of the memory element 65-1 and the fourth control input, the third match block skips the three least significant bits with the corresponding state

50 . 5 0 5 5 5

0

0

The scientific research institutes of the memory element 65-2, the third bit outputs of the circuits 66-2 and 66-3 are combined and together with the outputs of the remaining two low-order bits of the circuit 66-3 are the second output of the first recording resolution unit 20. The output of the memory element 65-1 is the third output of the first block 20. permission to write. The second recording resolution block 21 is an (FIG, 12) element AND 68, a memory element 69 and a resolution block 70. The inputs of the element .and signals from the second and third blocks. The output of the AND element is applied to the p-trigger input of the memory element 68, to the R-input of which a signal is supplied from the installation input block. The trigger output and the signal of the first control input are the enable signal for resolution block 70, which consists of four WESHANDES, but one step each bit, for one input of which a signal is output from block 69, and to other inputs - a signal from the first control input and the input of the second recording resolution unit 21, the output of which is. the outputs of the OR-NOT elements of the resolution unit 70, - The third block, the recording resolutions (Fig, 13) are two blocks 71 and 72 of the match, two elements: the memory element 73 and 74, the element NOT, the two elements OR NOT. When a match coincides with the first 71 or second 72 coincidence circuit, a short pulse is obtained at their output, which controls the trigger of memory element 73 or 74. Their installation in the initial state is produced by pulses from the setup input, which is connected to the R input of the flip-flops. The outputs of the trigger elements 73 and 74 of the memory are combined by R-SHI according to the diagram (Fig, 13). Fourth recording resolution block 23

(Fig. 14) represents two elements HE 81 and 82 and three blocks 78 - 80 matches, the outputs of which are OR-connected and are output of block 23. Signals of the second and first inputs of block 23 are fed to the inputs of the first block 78 of match, . signals from the third and inverted signals from the first and fifth inputs are sent to the second coincidence block 80; signals from the fourth, fifth and inverted first inputs of the block 23 to the third match block are shown. Pilot a signal 24 (Fig. 1 5) element {-BY / OR- 83, two elements 84 and 85 of memory, two elements OR-NOT 90 and 91, two blocks 86 and 87 matches, element NOT 88 two elements OR 89 and 92. A signal is supplied to the input of element 83 from the second control input of the pilot signal block 24, and its direct and inverse outputs are fed to the D inputs of the trigger of the memory elements 84 and 85, the C-inputs 84 are given a signal from the output of block 90, and the C-input 85 is fed OR connected to the block 92 of the signal of blocks 90 and 91. The R-inputs are supplied with a setting signal, outputs memory elements 84 and 85 are fed to coincidence blocks 86 and 87, the second inputs of which are fed from the first control input of block 86, the inverted signal from the first control input of block 87. The outputs of the coincidence blocks are ORed at element 89. The second delay element 25 (Fig. 16) is an address generation unit 93, two elements and 95 memories. , NOT element 96. The control unit 93 addresses the formation Wani JH its compounds with similar elements onto the memory as in the first delay member 6 (Figure 5). Element 96 controls the Write mode of reading the memory elements. -

The information transmitted to the communication channel depends on the results of the comparison of the four most significant bits of the corresponding samples, the corresponding lines in the second, third and fourth and fifth blocks 11-14 of the match, and is the result of two-dimensional processing of the original digital signal. Elements j and rows are transmitted to the communication channel through even counts with information about the true bit positions of the source code of the switch 4, the second input of which is connected to the second output of the second memory register 9. Elements (+1) -th row are transmitted to the communication channel by the switch 4 also through the readout information, depending on the comparison results: in the second comparison unit 12, the first and second inputs of which are fed from the second outputs of the second register 9 memory and summing register 7 memory, respectively

5 0 5 0 5 0 5

0

five

four high-order bits (j-l) -ro and (j + l) -ro samples of the j -th row; in the third block 13 of the comparison, the first input and the second input of which are fed four cTapmix bits from the second outputs of the second and first registers 9 and 8 of memory, respectively (i-l) -ro, of the j-th row and the 1st count (j + l) st line; in the fourth block 14 comparisons at first. and the second inputs of which are given four higher bits from the second output of the second register 9 of memory and. the output of the third register 10 memory, respectively (il) -ro and i-ro samples J - and lines, as well as in the additional comparison block 26, the first and second inputs of which are given four high-order bits from the second output of the second memory register 9 and output the second element of the delay, respectively, (1-1) -th count of j -th line and (1-1) -th countdown (+2) -th line. If, as a result of a comparison of (il) -ro and (i + l) -ro counts of the j-row, it turns out that at least one of the higher-order bits has changes, then (il) -oM count of the j -th row will be transferred information about the true state of five higher-order code bits. Information about the fifth bit will be transmitted along with information about the true state of the four higher bits by the fourth recording resolution block 23, the third input of which is connected to the second output of the second memory register 9, and the output connected to the third input of switching unit 4. In the i-th countdown (j + l) -th row, the true state of five bits of the source code will also be transmitted. If the fifth comparison block has the level of a logical unit at its output, it means that there are no differences between the four highest digits between (1-1) -th samples of the jth and (+2) -th line. In this case, the four most significant bits are transmitted by the switching unit 4, the fourth input of which is connected to the output of the second recording resolution unit 21, and the fifth bit will be transmitted in the same way as in the previous case. In this case, the recovery of the missing elements will be as follows: (1-1) -th countdown (+1) -th row is restored as 1th count J -and

lines a –and count j –and lines the same as; -and countdown (j + l) -ft lines. If the output of the fifth block 26 compares the level of logical zero, which indicates the presence of changes in at least one of the four high-order bits of the corresponding samples, then two more comparisons must be made: (il) -ro count-и lines and 1-g readings (j + l) -A lines in the third, block 13 comparison and (il) -ro and .th counts j - lines in the fourth block 14 comparison. If at the second output of the third block of comparison the logical zero level, the presence of a change, then in the / th count. (d +) - th line will be transmitted the information about the true state of the four most significant bits of the source code by the second recording resolution unit 21 through the switching unit 4 and additional information about the recovery nature of the missing elements. a pilot signal 24, the fourth control input of which is connected to the second output of the third recording resolution unit 22. The nature of the additional information O or 1 depends on the result of the comparison in the fourth block 14 of the comparison. If between (il) -th and t-th readings of the j-th line there are differences in older digits, then additional information about it indicates that the recovery of the missing elements will be: (il) -and (j + l) -th line and 1th count J -and lines are the same as the 1 st count (s + 1) -th row. If at the output of the fourth block of matching the level is a logical zero, the absence of changes, then additional information 1 indicates a different nature of the recovery of the missing elements: (il) and countdown (+1) lines and (i-L) -th countdown j the rows are recovered as (il) -and counting the J -and lines. In this case, the signal from the second output of the third comparison unit 22 on the fourth control input of the first recording resolution unit 20 will prohibit the transmission of information about the third bit in the t-th count (+ 1) -th row.

If the output of the second block 12 compares the logical O level — the absence of changes in the higher bits (il) -ro and (i + l) -ro of the J-row samples, then the information transmitted in the f-th count will depend on the results comparisons in the third 13 and fourth 14 comparison blocks. If at the first output of the third block 13 of the comparison, the logical O level is the absence of changes, then in the 1st count (+1) line the information about the true state of the three next highest bits of the (il) th count j will be transmitted and lines from the output of block 19 of the lower-order memory at the third input of switching unit 4, and information on changes in the characters of the lower-order bits (nd count (+) -th row relative to (il) -th count j, and the strings also in block 4 switching, the first input of which is connected to the output of the encoder 16. The signals from the output of the third the recording resolution block 22 and the third output of the first recording resolution block 21 will allow a quarter block of the recording resolution block 23 to which they are connected (first and fifth inputs respectively) to write the lower bit from the output of the lower bit memory block 19 to the block memory 4 switches in (il) -th and 1st samples. If there are no changes in the four high-order bits (il) -Fo and (i + l) -ro samples of the j-th row, and as a result of the comparison in the third block 13, (il) -th reference of the jth row and the 1st reference of the (r + 1) -th row are differences, then the transmitted information depends on e - comparing the result of (i-l) -th and i-th sampling, j -fi rows in the fourth block 14 of comparison. If the output of the fourth block 14 compares the level of the logical unit, which indicates the presence of changes in the higher bits, then in the i-th count the information1 will be transmitted to the communication channel; the true state of the four most significant bits of the 1st count () -th row from the output of the second block. 21 of the recording resolution and the pilot signal unit 24 will generate an additional combination 10, which will be transferred to the communication channel by the switching unit 4 via the fourth recording resolution unit 23. In all cases, the recovery of the missing elements will be: (i-i) -th countdown (s + 1) -th frame

ki is the same as (1-1) -th countdown of the j-th row, and the 1st count of the j-row is the same as m -th count (h + 1) -th row. If the output of the fourth comparison block 14 is the logical zero level (no changes), then in the 1st readout, the true state of the four most significant bits of the 1st Count will be transmitted in the communication channel and the pilot block 24 will generate a code pattern 01 , the first bit of which will be transmitted in the (i-1) -th count of the J-th row, and the second one - in the h-th count (C + 1) -th row. Restoration of missing elements on the receiving side: (1-1) -th countdown (g + 1) -th row will be restored as 7th counting +1) -th row, and - {- and counting J-th row - as ( i-1) -and counting J -and lines. I. - -.

As a result, when the input analog signal enters the inputs of the reference level setting unit 1 and the analog-digital conversion unit 2, the selector of the reference level setting unit 1 removes synchromesh from the analogue signal, and the multivibrator connected in series with the selector produces on the leading edge of clock pulses which are used to set the entire device back to its original state. For this, the setting pulses are sent to the R-inputs of the memory element trigger of memory block 18, the installation inputs of the address generation circuit counters of delay elements 6 and 25, the R-input of the clock divider trigger trigger of the control unit 3 and the C-input of the divider trigger line frequency to obtain a half-line frequency (Lig.Z). At the same time, the same pulse is applied to the input of the synchronization code generator 5. During this pulse, the synchronization code generator generates special code quotes that mark the beginning of the line. These channels are transmitted to the channel by the switching unit 4 via the encoder 16. The analog-to-digital converter of the analog-to-digital conversion unit 2 (Fig. 2) converts the input analog signal into a digital form. A seven-bit parallel code is fed to the output of an analog-to-digital conversion unit 2

five

j Yu 15 0

5 o 5

0

0

five

with a clock frequency determined by the Kotelnikov theorem depending on the upper bound; frequency of the converted signal.

t

The clock frequency arriving at the clock input of the block serves to start the counters of the address of the driver of the address of the delay elements 6, 25 and to obtain a half-clock frequency in the control block 3 (Fig. 1-8). Delay element 6 records information about the states of bits the output of the analog-digital conversion unit 2 during the negative half-wave of the half-line frequency at the control input of the delay element 6 (Lig.5) and allows reading information during the positive half-wave. Thus, at the inputs of the summed 7 of the memory (FIG. 6), we simultaneously have information about the (i-th) -th row from the delay element 6 and information about the j -th row

from the output of block 2 analog-to-digital conversion. Control signals

; on the first, second, and third control inputs, it is possible to write even samples (strings and odd samples () of the second row (Fig. 19)) to the memory elements by means of block recording enablers. At the same time, the combination on the first and second control inputs The third memory register 10 inputs will allow to write information about the four high-order bits of odd samples of the j-th line into it.Synchronization of writing to all memory registers, as well as synchronizing operation of the entire device, is performed by synchronizing pulses from the first, second, tert of the first, fourth, and fifth sync outputs (Fig. 18) of the control unit 3. The control output of the control unit 3 is used to reset the memory elements of the first 20, second 21 and third 22 write resolution blocks and pilot block 24. from the output of the summing register 7, the memory is copied sequentially into the first 8 and second 9 memory registers. Thus, there is information about (ii) -OM count j and the row (second register 9 memory, i-th count (+ 1) -th line (first register 8 memory), (i + l) -OM count

The jth row (summing register of memory 7), the four most significant bits of the Vth reference of the jth row (third register of memory 10). In this case, the second delay element 25 stores information from the previous cycle — the work on the four high-order bits (i-l) -ro of the countdown (j + 2) -th row. The delay for a time equal to the length of two lines allows two to occur (Fig. 16) of memory elements 94 and 95.

Further operation of the device depends on the results of the comparison in the second 12, third 13, fourth 14 and an additional 26 blocks of comparison.

If the first output of block 12 compares to the first and second inputs of which four high-order bits are supplied from the second outputs of summing register 7 of memory and second register 9 of memory, respectively, the level is logical O, which indicates the presence of changes in at least one of the oldest bits, and at the output of p of the comparison block 26, to the inputs of which four higher bits are fed from the output of the second delay element 25 and the second output of the second memory register 9 (il) -e samples Cs + 2) -th and / - Th lines, the level of logical units (no meas neny), the first block 20-resolution recording (11) through the blocks 66-1 and 66-2 matcher (Figure 20) zaprppet in memory unit 18 information about the true state of the five rows of the discharge source. At the same time, the remaining two low-order bits will be set to the state in accordance with the received algorithm on the feedback ring: the second output of the memory block 18 is the second input of the memory control block 17 - the memory block 18. The installation of the two least significant bits will be made by the installation blocks of the lower order bits (FIG. 8. The blocks 56-1, ..., 56-8 of the prohibition choose the oldest of the bits. In which the change occurred: while recording the true state of five bits The code sets, and the outputs of blocks 57-3 and 57-4 of the installation of young gaps are set to ft and S inputs of the trigger elements of the memory elements (Fig.9) through the elements OR such

Since the older of the changed bits, O - 1, changes in the state, the lower order bits are set to 5 and vice versa. At the same time, a fourth resolution block 23 (FIG. 14) records the third input of which information about the third bit 10 de 10 and the fifth input of the first resolution resolution block 20-1 is entered into the communication channel. records, from the second output of the second register 9 of the memory will also be transmitted information about the true state of five bits of the code. Since this comparison result in the second comparison block 12 is stored on the memory element 65-1 in the first resolution block 20 20. recording two readings, then in the next reading the nature of the device’s operation is preserved. It should be taken into account: there is, that when comparing the four high-order bits in the second block of 25 k 12 comparisons, as in the fourth 14 and fifth 26 blocks of the comparison, the comparison occurs taking into account prohibited changes. The forbidden changes are determined by block 53 (Fig. 7) 0 of block 12. The forbidden changes are considered to be the characters of the most significant bits between two readings of the following type:

 1000-0111, 0111-1000, 0100-0011, 5 0011-0100, 1100-1011, 1011-1100, 0010-0001, 0001-0010, 0110-0101, 0101-0110, 1010-1001, IOOI-10 IO, inO-llOJ, 1101-1110 and all changes in the youngest of the four most senior 1) bits.

If the output of the fifth block 26 compares the level of logical zero (the presence of changes, then the information transmitted in the i-th countdown (h + 1) -th

five

the rows will depend on the result of the comparison (i-l) -ro of the reference of the J-line and the 1st reference of the (+ 1) -th line, which is produced by the third block 14 of the comparison. If in these

counts there are changes at least in one of the higher bits, then in i-OM the count of the j line will be transmitted information about the true state of the four high bits of the second

a recording permission unit 21 (Fig. 21). The fifth bit of this codecoding will be used to transmit additional information depending on the result.

Comparison in (1 -) - ohm and rh sample is so J - lines. To do this, in the third recording resolution block 22 (Fig. 13), the signals will coincide and the memory element 74 will operate. The signal from the second output of this block will prohibit the transmission of the third bit to memory block 18 and to the communication channel. For this, the second output of block 22 is connected to the fourth control input of the first recording resolution block 21, and at the same time will allow the additional code combination to be written to the block 24 pilot signal. Additional information is transmitted in the form of O, if there is no difference between (il) -biM and i-th samples of the J-th line, otherwise it is transmitted 1. If the second comparison unit 12 says that there are no changes in the four high-order bits ( the logic level O at the second output and logical J at the first output, then the operation of the device will depend on the result of the comparison in the third comparison block 13, to the inputs of which four senior bits are respectively fed from the second outputs of the first 8 and second 9 memory registers. first exit third About Comparison Unit 13 Logic level O (no change), that in the first recording resolution block 20 on the AND 64-2 element the corresponding signals will coincide and the trigger of the memory element 65-2 will allow the block 66-3 to allow the match in the memory block 18 In addition to the four high-order bits, which are recorded via block 66-1, the next three bits of the next highest order (Fig. 20. At the same time, the same three bits will be written to the lower bits memory block 19 and from its output in the next count information about these bits will be transmitted to anal communication switching unit 4, the third output is connected to the output of memory 19 LSBs. Moreover, the fourth recording resolution block 23 transmits a record of information about the third bit of communication to the communication channel twice, in this and the next reading.

Permissive signals are signals from the third output of the first recording resolution block 20 and output

the second block 21 write resolution. Together with the information about the three least significant bits in the next countdown, 5 information about changes in the characters in the three least significant bits will be transmitted. To do this, in the first comparison unit 11 (Fig. C), the three lower bits of the memory block 18 and the second memory register 9 are compared. Information about all changes from the output of the first comparison unit 11 is fed to the input of the transmitted symbol selection unit 15, which selects the oldest among the changed bits, and then, through the memory management unit, sets the low-order bits to the corresponding state . The cipher 16 encodes the number of the changed bit with a binary code and transmits to the communication channel by the switching unit 4. If the third comparison block indicates the presence of changes in at least one

5 out of four older bits then

the operation of the device is determined by the quarter-unit comparison unit 14, to which four high-order bits are fed from the second output of the second register 9 of the memory and the output of the third register of the 10 memory. This situation is identified by the AND element (Fig. 22) of the second block 21 (Fig. 12) of the recording resolution and is stored by the memory element, which permits the recording of information on the four most significant bits in the memory block 18 and to the communication channel via switching unit 4, the fourth input of which is connected to the output of the second unit 21

0 write permission, in this and follow /

Countless counts regardless of the output of the fourth comparison unit 14. The output signal of the fourth comparator unit 14 is used to form additional code combinations in the pilot signal unit 24 (Fig. 15 |. To do this, a signal is output from the output of the fourth comparator unit 14 to the input of the D-flip-flops of the memory elements. Sync signal

0 to the C-input of the trigger arrives with the appropriate resolution from the outputs of the third recording resolution block. Thus, if at the input of the fourth comparison block the level of logical zero and the third control input also have a level of logical zero, then additional code information 01 will be recorded in the memory elements (Fig. 24), otherwise - 10 through the fourth write enable block to the switching unit 4 sequentially: the first bit of the additional code combination in one sample, the other bit in the other. If the resolution is present at the fourth control input, then additional information in the form of O or G, depending on the signal at the second control input of block 24, is written to only one element and is transmitted, respectively, only in the second count,

The table below shows the algorithm of operation of the digital video signals.

Claims (2)

Claim A device for compressing digital television signals on the author, St. No. 1146831, characterized in that, with a purpose: to reduce the distortion of television signals, an additional delay element and an additional comparison unit are introduced into it, wherein the information input The delay element is connected to the second output of the memory unit, the setup input is connected to the output of the reference level setting unit, the clock input is connected to the clock output of the analog-to-digital conversion unit, the control input is from the nepBbtNt output of the control unit, and the code is. with the first input of the additional unit comparison, the second input of which is connected to the second output of the second memory register, the output is connected to the first additional control the input of the third recording resolution block, the second additional control input of which is connected to the output of the fourth comparison block, the third additional control the input is connected to the first output of the third comparison unit, the additional installation input is connected to the installation output of the control unit, the additional synchronous input is connected to the fourth sync output of the control unit; the auxiliary output is connected to the auxiliary control input of the first recording resolution unit and the auxiliary control input of the pilot signal unit. Thebes.2 Gakgpobyy byhy SJk8i .JJO, iej9 jk.ZO, Zi, 2Z, 24 Outputs on the way to nacmomoi Vshoda polostrochnoi Ustanobka frequency 20, Zf, 2Z, 2 % r5 3rd run  bypass 4th byd 2nd bhoU Nuprabl.by 2 - U tinpa6 / SxQd 5-uSxod Sync run 52 seconds 44-f Szvsbu Upra6 / u {cchy move entrance  WITH Dg 44- 44-j sg  DDS & nd % L l 6-l I d W-JTJ Guided stroke t i-uyt S / Jj Sxod 2nd Supra / Yanschy Sxod The inputs. Smofou Perby.  I Sunbrood 50-f 50-2 4S -r GR 5GG 1 51 I a FIG. a Second item 5iiixodb Perdy Sxod one Second Journey I FIG. 7 ttfttiu falling in / leek 9 Sho L Sunshine ynpa6 / ffftotnuu d) (0d with CK and but Vytd . 3rd Run one with Cg JO with c ,, y but but Phage.U. Shit, i1 2nd exit 1-0. abradl - 2.-U 3rd Synchrobhad, tu III Installed. entrance entrance FIG. (2. , , Z-yu ri & n w, i 3-i1m em1osh, and Sxoa bjo Sieve Outflow Shioihod 1- & nagged for o- til w, w Log in T HcmaHoBovHbiu ixef 771Ap / Ja " .,. Vb1ho9 Fili 1 stanabachnych Z-Uupra6 / 7uschy bhad 3rd ynpaS / jff- di di Sxod fa ynpaSjjff yush.i Sxod 7th bhad Boixod FIG. 15 21 / Lwsm.  H i ... KKcvemtf Kty tdnae invention ® - riefieffaSaennfe sflfftfKinot architect .   7 ; ... "p ../ mg nwm L i I I f ... the check 9sa.f (mpeSa№ «} e} u3aSpa fnc e