SU1234968A1 - Sine shift signal-to-digital converter - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used to connect analog information sources with a digital computing device. In order to increase the reliability of a converter by monitoring its performance before starting operation, the sine-wave and cosine signals from a displacement sensor through threshold drivers 1 and 2, respectively. , are fed to the inputs of the memory block 3, made in the form of a shift register, the clock input of which is connected to the generator 5 pulses. At the output of block 3, four sequences of rectangular signals are formed, the relative position of which is determined by the direction of movement, i.e. the sequence of input signal changes of the threshold formers 1 and 2. The decoder 4 in the first converter operation belt forms the output signals of the unit 3 of the limpile sequence in the increment of the transform Sl tsD CO 4ik 0 C5

Description

Places on one of the two entrances depending on the direction of travel. To determine the operability of the converter, a frequency divider 7, a trigger 8, an AND element 9 and a control register 6 which determines the converter operation in the monitoring mode or in the measurement mode are entered into it. In the control mode from the intermediate output of the divider 7 to information, the Invention relates to automation and computing and can be used to connect analog information sources with a digital computing device.

The aim of the invention is to increase the reliability of the converter.

Figure 1 shows a block diagram of a converter; in fig. 2 is a timing diagram of the operation of the converter with a motion sensor, mode 1; in fig. 3 - time diagram of the converter control, mode 2.

The converter contains the first I and second 2 threshold drivers, whose inputs Bx.1 and & X.7 are information inputs of the converter, and outputs L and B are connected to the first and second information inputs of memory block 3, the first A, and the second B The outputs of which are connected to the first and second information inputs of the decoder 4 and to the third and fourth information inputs of block 3, the third A, and fourth To the outputs of block 3 are connected to the third and fourth information inputs of the decoder 4, the first Out.1 and the second Out. The 2 outputs of which are the outputs of the converter, the pulse generator 5, the output of which is connected to the first clock input of block 3, the inputs of control register 6 are the control inputs of the converter, the first register code 6 is connected to the control input of block 3, the second and third outputs are to the first and second control inputs of the decoder 4, the fourth output, to the reset input of the divider 7, the clock input of the unit 3 receives pulses, simulating the increment of movement, and through element 9 I receive the clock pulses. At the end of the test cycle, a certain number of pulses must be received for the converter, which is compared with the calculated one, and the efficiency of the converter is determined by comparing the result. 1sptff, Zil ,, 1 table.

volts, to the first input of the trigger 8, the fifth output to the reset input of unit 3, the group of outputs to the control inputs of the higher bits of the divider 7, the output of the generator 5 pulses connected to one input of the element 9 And and to the information input of the element 7 frequency, the first output of which is connected to the fifth information input of block 3, and the second output to the second input of trigger 8, the output of trigger 8 is connected to another input of element 9 I, the output of which is connected to another sync input

3 memory block.

The decoder 4 contains the first 10 and second 11 elements EXCLUSIVE OR, the first 12 and the second 13 inverters, the first 14 and the second 15. And elements, the first

and the second inputs of the element 10 are the first and fourth information inputs of the depotfrater 4, the first and second inputs of the element 11 are the second and third information inputs of the decoder 4, the output of the element 10 and the output of the element 11 through the first 12 and second 13 inverters are connected to the first inputs with and D, the first 14 and 15 elements And, the second inputs of which

are connected to the outputs by element 11 and 10, respectively, the third inputs are included in the first and second control inputs of depfractor 4, and the codes of elements 14 and 15 are the first and

second, the outputs of the decoder. 4. The first and second frequency divider 7 codes are designated F and G-, the trigger output 8 -G, the fourth register code 6 - N.

The Converter operates as follows.

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in the record of the bridge from the control codes (CC) entered in the register 6, the transmitter is configured to work in one of the modes 1 or 2 in accordance with the table.

The conversion of information from displacement sensors consists in converting sinusoidal displacement signals into meanders, generating short counting pulses, of which at one of the outputs, the first or second, depending on the direction of movement.

After supplying the control converter to the control register 6, the CC1 code is entered, according to which the memory block 3 is configured to receive information in the directional code from the first, second, third, fourth inputs on the GI clock pulses coming from the generator output 5 pulses per first - the new clock input Ti of the memory block 3, and the transmission of information is permitted through elements 14 and 15 AND of the decoder 4 to the Out. 1 or V2.2, depending on the direction of movement, respectively. Logical units on the fourth and fifth outputs of the control register 6 keep in the initial (zero) state the divisor 7 and the trigger

After entering into the control register 6 of the code UK2,: the converter starts operating in mode 1. A logical zero at the input R of unit 3 allows the memory unit 3 to receive information through the parallel input inputs D, D, D, .D. Threshold formers 1 and 2 transform the input, 90 ° shifted sinusoidally modulated movement measured signals into square impulses (meanders), A and 5 (Fig. 2). The information on the first and second inputs is recorded in block 3. ti on the leading fronts (the transition from the level of the Logical zero to the level of the logical unit) of the clock pulses GI (Fig. 2A, B). The output pulses A2 and BZ of memory block 3 repeat the pulses at outputs D and B. Respectively, with a delay of GI clock pulses by a period of time.

The decoder 4 processes the signals from the outputs of the memory block 3 in such a way that during a direct run, the levels of the logical unit at the inputs of element 14 And in one period of the input signals coincide four times. On the first

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bp, | during the process of exploding, the short counting pulses with a duration of one period of GI clock pulses form. At the inputs of the second element 15 And the level- 5 mi of the logical unit during the direct course do not coincide, hence the pulses at the second output are not formed. During the reverse course (reverse,:, motions), on the contrary, the levels of logical 10 units at the inputs of element 14 do not match, the coincidence occurs at the inputs of element 15 I. At the second output, short counting pulses are formed (in one period of input sig tal 5).

In mode 1, frequency divider 7 and trigger 8 are held in the initial state.

Mode 2 is used to determine the operability of the input circuits and the decoder 4, as well as digital information processing units, the inputs of which connect the first and second inputs of the converter 25 (not shown in Fig. 1). In digital information processing units, either reversible counters or the rear conventional accumulating counters are used as receivers of the unitary code C of the first and second outputs. In the first case, one reversible counter is used, information in which is supplied, respectively, to the input of the summation and the input subtraction of the NIN. The code for the magnitude of the shift is removed from the counter output. In the second case, information about the movement in the forward and reverse directions is recorded in different counters;

This code is the magnitude of the displacement is 40

It is obtained by subtracting the codes recorded in the corresponding counters. Consequently, there are two algorithms for the formation of testing pulse sequences at the first and second outputs of the converter.

In the first algorithm, after the UK1 code (FIG. 3), which holds the converter in the initial state, the CDM is entered into the control register 6. In this case, logical zeros on the first, third, fourth and fifth outputs configure memory block 3 to receive (with a shift) the sequential code on the fifth 5th input W on the front edges of the clock pulses at the output of element 9 AND, prohibit the information 15 And on Exit. 2, allow work

35

five

divider 7 frequency and trigger 8, respectively. On the back fronts (transition from the level of the logical unit to the level of logical zero) of the sync pulses (FIG. 3), the GI information on the first output (from the third bit) of the divider 7 is changed to the opposite one after every four periods, and periodically filled with ones and zeros (Fig. 3, A, A R, B,) while the decoder 4 generates on Out. 1 (2 -1) counting pulses, which are recorded in the reversing counter of the digital information processing system

After the arrival of the N-ro pulse (Fig.ZD) at the input of the higher bits of the frequency divider 7, a pulse is formed at its output (Fig. 3F), flip-flop trigger 8 (Fig. 3 &) to the opposite state, prohibiting the flow of GI clock pulses through the element 9 And on the second one, the input T of the memory block 3. The process of forming the normalized number of pulses stops.

In a similar way, the decoder 4 and the reversible counter of digital information processing with Q4 are checked, when the pulses are generated at Ex 2, and the reversible counter is working on the subtraction. With the division factor, N is subtracted () pulses. In the second algorithm, CC 5 is entered into control register 6 and logical units at the second and third outputs of register 6 are allowed to be simultaneously formed at Output. 1 and Ex. 2 counting pulses in the amount of (), Thu register counters of the digital information processing system.

In order to enumerate all possible states of the system counters. processing of digital information, the division factor of the N higher reserves of the frequency divider 7 is equal to: N (K + t (/ 2, where -K is the counter capacity, if K is an odd number, and M (K + 1) / 2 + 1, where (K + 1) / 2 is a partial part of the private if K is an even number. In the first case, the number of pulses is equal to the counter capacity, in the second - one more.

As a result of the control of the transformation of the bodies, the reliability of his work becomes worse. The frequency of the counting pulses in the chip times smaller than the frequency of the clock pulses GI, but it is several

.

, - J Q .. to. five

20 25

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five

35

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g orders are higher than the maximum possible frequency of signal inputs at the inputs Bx, 1, and Bx, 2 in mode 1.

Claims (2)

1. The transducer of sinusoidal motion signals into a code containing the first and second threshold drivers, the inputs of which are the information inputs of the converter, and the outputs are connected to the first and second information inputs of the memory block, the first and second outputs of which are connected to the first and second decoder information inputs and to the third and fourth information inputs of the memory block, the third and fourth outputs of the memory block are connected to the third and fourth information inputs of the decoder, the first and second outputs of which are the outputs of the converter, a pulse generator, the output of which is connected to the first synchronizing input of the memory unit, so that to increase the reliability of the conversion, a control register, a frequency divider, a trigger and an AND element are entered into it, the inputs of the control register are the control inputs of the converter, the first output of the control register is connected to the control input of the memory block, the second and three the outputs to the first and second control inputs of the decoder, the fourth output to the reset input of the frequency divider and the first trigger input, the five output to the reset input of the memory unit, and a group of outputs to the control inputs of the high-end splitter frequency, the pulse generator output is connected to one input of the AND element and to the information input of the frequency divider, the first output is connected to the fifth information input of the memory unit, and the second output is connected to the second trigger input, the output of the trigger is connected to another input of the I, O output One of which is connected to the second synchronizing input of the memory unit. 2. The transducer according to claim G, O T - l and h and y and the fact that the decoder contains the first and second elements EXCLUSIVE OR, the first and second inverters, the first and second elements And, the first and second inputs of the first element EXCLUSIVE OR are the first 712 and the fourth informational inputs of the decoder, the first and second inputs of the second element SPEAKER AIP are the second and third informational inputs of the decoder, the outputs of the first and second elements EXCLUSIVE I.PI through the first and second inverters respectively connected to the first UK1 In the table, the following notation is accepted: X is an arbitrary output state; 1/0 - high / low logic output state; N is the division factor of the frequency divider 7; () - the formation of pulses only at the first output; (-) - the formation of pulses only at the second output; (+/-) - the formation of pulses at the first and second outputs, depending on the direction of movement or the test mode. OSpamHi / tf xOf 3.9688 the inputs of the first and second elements are And, the second inputs of which are connected to the outputs of the second and first elements 11SOLVIEW OR, the third inputs are the first and second control inputs of the decoder, and the outputs of the first and second elements AND are the first second outputs of the decoder. Installation - Initial feSspc n / isMOU move e "v 81 i De -Sr e s- t, in, Smj omt / L .V-v IrCifs L / 1  I1rn1 TT T- T 1. ai M rri ± mijjit H .З Editor K. Voloshchuk Compiled by A.Smirnov Tehred O. Gortvay Proofreader M. Demchik 2990/58 Circulation 816 Subscription VNIIPI State Committee-USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4