SU1239710A1 - Arithmetic unit - Google Patents

Abstract

The invention relates to digital computer technology and can be used as part of both specialized computers and general purpose computers. The purpose of the invention is to increase the speed by combining in time the implementation of individual elementary operations. The goal is achieved by the fact that in the arithmetic unit, each bit of which contains four triggers, sixteen elements AND and six elements OR, the seventh element OR and the element NOT with corresponding correspondences are additionally inserted into each category. 2 Il. 00 with Nl

Description

The invention relates to digital computing and is intended for use in digital computers.

The purpose of the invention is to increase speed.

Figure 1 shows a functional diagram of two binary bits of an arithmetic device; figure 2 - the timing diagram of the arithmetic unit.

The discharge of the arithmetic unit contains triggers 1-4, elements AND 5-20, elements OR 21-27, - element NOT 28 clock inputs 29-31 devices ,, device transfer input 32, clock inputs 33-36 devices, information input 37- devices.

Arithmetic unit operates as follows.

Let us consider the work on the example of performing the operation of addition of two positive numbers represented in binary code. Prior to the first addition operation, all the device triggers are set to the zero state by applying to zero, the trigger inputs of the actuating impulse (to simplify Fig. 1, the trigger setting inputs are not zero). The first addendum enters at input 37 and enters the triggers 3 of all bits by applying a pulse to input 35. The impulse along the circuit of the elements AND 19, OR 23, AND 15, - OR 26 enters the single input of trigger 3 and sets it to the single state. If at the input 37 there is no potential corresponding to the unit code, then the trigger 3 does not change its initial state. The first term is now stored in triggers 3, and the code of the second term is received at input 37.

During the first time tick (t), the code is transferred from triggers 3 to triggers 2 and 4, for which pulses are fed to inputs 30 and 34.

At the second time tick (tj.), The first modulo sum of the two codes of the first term stored in triggers 2–4 and the code of the second term arriving at input 37 is performed. To do this, input 35 is pulsed. In those binary bits in which 37 is input

39710. 2

there is no potential corresponding to the code; dinits, impulse along the circuit of elements And 19, HIM 23 is fed to the inputs of elements And 14 to 15 and inverts the code stored in trigger 3.

If the unit code is stored in triggers 3 and 4 before the second clock pulse arrives, then the pulse from the output 0 and the element 14 through the element OR 24 of the most significant bit arrives at the second input of the element 20 and the first input of which receives a pulse through the chain of elements AND 19 and OR 27. Thus, even before triggering switches 3 and 2, the second pulse generates a transfer signal from this bit to high bit, which increases the speed of the device.

20 If, prior to the arrival of the second one-shot pulse, trigger codes 2-4 store a zero code, and the code of the second term in this bit is equal to one, and a transfer signal is formed in the lower order bit. 5 then in this category it is necessary to ensure distribution. transfer to the next (senior) bit This is achieved by applying a second clock pulse through the circuit.

30 elements AND 19 and OR 27 at first. the input element AND 20, which allows the transfer signal arriving from the lower half of the bit, through the elements OR 24 and AND 20, to propagate to the side of the older bits in the time period tj ,. After a time equal to the duration tj, the propagation of the renorisation signal through this bit is controlled by the trigger p 2,

40 since this trigger is set by the impulse c-to one state. In this case, the executive impulse passes through the chain of elements And 19 and OR 22. OrNseTHM is another feature of the work during the execution of the first addition modulo two.

If the triggers 2-4 store the code zero, the code of the second term is equal to one, and the transfer from the younger one is yes and no, then the second impulse, through the circuit of elements 19 and 19 and 27 received at the first input of the element 20, could flow In the higher order, if the zero output of the trigger 3 would directly be connected to the input of the element OR 24, to eliminate the possible failure of the second executive pulse through the element HE 28

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enters the WHR element I 12 and prohibits the work for the duration of the second pulse.

In the third time step (tj), the result 5 of the first addition modulo two, stored in flip-flop .3, is sent to flip-flop 4. This is necessary to prepare the execution of the second addition modulo two. Simultaneously with the transfer of the code from the U of the trigger 3 to the trigger 4, the potential of the end-to-end transfer continues to form.

, In the fourth time step (n), upon completion of the distribution of maximum transfer 15, an input is given to input 36. In those bits in which the through-transfer potential enters the input 32 of the least significant bits, a pulse is passed through the circuit of elements 20 AND I1 and OR 23 to the inputs of elements AND 14 and 15 and performs the second modulo two addition. The fourth clock completes the add operation of two codes.

The operation of code subtraction is carried out similarly to the above implementation of the addition operation. The difference is that, by the second time step, the inverse value of the codes from input 37 is applied to the inputs of the trigger 3.

The code multiplication operation is performed by successive additions of the code stored in flip-flops 3 and 4 35 and the code that pushes input 37, and shifts the codes right by one bit. The shifts of the codes by one bit to the right are performed in two time slots. On the first clock the code from the triggers. 1 is poured with a shift of one bit to the right to trigger 2. To do this, a pulse is applied to input 31. In the second clock cycle, the number code stored in. Triggers 2 are sent to Triggers G. A pulse is applied to input 29 to do this.

The code shift in trigger ah 3 and 4 is implemented in a similar way. The only difference is that the transfer of the code to the triggers 4 is performed without shifting, and the transfer of the code to the triggers 3 is performed shifting by one bit to the right. To accomplish this, pulses are successively applied to inputs 34 and 33,

10 4.

Provided that the multiplier code is stored in triggers 1, the multiplicand code is fed to input 37, and the triggers 3 and 4 are set to the zero state. At the first stage of performing the operation, the trigger code 1 is shifted to the right until the unit code appears in the last (least significant) discharge. After that, the code shifts are stopped and the addition operation is performed with the code arriving at input 37. The addition operations of the codes during the execution of the multiplication operation are identical to the individual addition operation considered above. After the addition operation is performed, the codes stored in the triggers will be shifted up to one at a time. If, after performing the shift codes by bit to the right, the unit code is again stored in the last bit, the operations of addition followed by the same shift are repeated. If the zero code is stored in the last bit, then only the shift codes of the adder triggers are performed. Shifts and additions Repeat until the number of shifts is equal to the number of binary bits of the multiplier. It should be noted that the supply of the necessary pulses to the clock inputs of the device is provided similarly to the prototype by known means.

An arithmetic unit, each bit of which contains four triggers, sixteen AND elements, six OR elements, and in the discharge zero and single inputs of the first trigger are connected, respectively, to the outputs of the first and second AND elements, the first inputs of which are connected respectively with inverse and forward the outputs of the second trigger, the zero and single inputs of which are connected respectively to the outputs of the first and second elements OR, the first and second

the inputs of the first element OR are connected respectively to the outputs of the third and fourth elements AND, the p. and the second inputs of the second element OR are connected respectively with the outputs of the fifth and sixth elements AND, the outputs of the seventh and eighth elements AND are connected respectively to the first inputs of the third and fourth elements

IHSh, zero and single inputs of the third trigger are connected respectively to the outputs of the fifth and sixth elements OR, the first and second inputs of the fifth one-element OR are connected respectively to the outputs of the ninth and tenth elements And, the first} and the second input the sixth element OR are connected respectively to the outputs of the eleventh and twelfth elements AND, the first, the inputs of the tenth and eleventh elements AND are connected respectively to the direct and inverse outputs of the fourth trigger, zero and. single the inputs of which are connected respectively to the outputs of the thirteenth and fourteenth elements And, the inverse output of the third trigger is connected to the first inputs of the third, eighth and thirteenth elements And, the direct output of the third trigger is connected to the first inputs of the sixth and fourteenth elements And, the second inputs of the tenth and the eleventh AND elements are connected to the output of the third OR element, the second input of which is connected to the output of the fifteenth element I, and in the device the inverse and direct outputs of the first trigger of each bit Yes they are connected respectively with the first inputs of the fourth and. the fifth elements of the adjacent low bit, the inverse and direct outputs of the fourth trigger of each bit are connected respectively to the first inputs of the ninth and twelfth elements and the next low bit, the first inputs of the fifteenth elements of all bits are the information input of the device, - the first, second, third, fourth, fifth, sixth and seventh clock inputs of which 5 are connected respectively with the second inputs of the first and second elements And, the second inputs of the third and sixth elements And, the second inputs the fourth and fifth elements And,

10 second inputs of the ninth and twelfth elements And, the second inputs of the thirteenth and the fourteenth elements And, with the second input of the fifteenth element And and with the first input of the seventh 15 element And each bit, the fact that, in order to improve speed, each bit contains the seventh element OR and the element NOT, and in each

20 rade de the second entrance

element AND through the element is NOT connected to the second input of the eighth element AND, the output of the fifteenth element AND is connected to the third input of the second element of the IGI and to the first input of the seventh element, OR, the second input of which. connected to the direct output of the second trigger, output, fourth and seventh elements OR are connected respectively with the first and second inputs of the sixteenth element AND, and the device output of the sixteenth element AND of each bit is connected to the second input of the fourth ILI element and

35 with the second input of the seventh element AND of the neighboring most significant bit, the output of the tenth, element AND of each bit is connected to the third input of the fourth element OR the next most significant bit.

40 r yes.

figure 1

t2

Forwarding code from TRZ 8 TRCH-fnepBafl)

Adding codes for Mazulng 2 (first)

Formation of transfer potential.

Forwarding code from Tr. 3 6 Tr. (vyurel,

Adding codes by modulofoZ (second)

Editor E. Papp

Compiled by A. Klyuev Tehred L. Oleinik

Order 3397/49 Circulation 671 Subscription

VNIIPI USSR State Committee,.

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, st. Project, 4

.2

Proofreader E.Roshko

Claims (1)

Claim An arithmetic device, each bit of which contains four triggers, sixteen AND elements, six OR elements, and in the discharge the zero and single inputs of the first trigger are connected respectively to the outputs of the first and second elements AND, the first inputs of which are connected respectively to the inverse and direct outputs of the second trigger whose zero and single inputs are connected respectively to the outputs of the first and second OR elements, the first and second inputs of the first OR element are connected respectively to the outputs of the third and h tvertogo elements and · first and second inputs of the second OR gate connected respectively with outputs pyato55 'th and sixth AND gates, the outputs of the seventh and eighth AND gates respectively connected to first inputs of the third and fourth members OR, the zero and single inputs of the third trigger are connected respectively to the outputs of the fifth and sixth elements OR, the first and second inputs of the fifth-element OR are connected respectively to the outputs of the ninth and ninth elements AND, the first and second inputs of the sixth element OR are connected respectively to the outputs of the eleventh and the twelfth element Ή, the first. the inputs of the tenth and eleventh elements AND are connected respectively to the direct and inverse outputs of the fourth trigger, zero and. single. the inputs of which are connected respectively with the outputs of the thirteenth and fourteenth elements AND, the inverse output of the third trigger is connected to the first 'inputs' of the third, eighth and thirteenth elements And, the direct output of the third trigger is connected to · with the first inputs of the sixth and fourteenth elements And, the second inputs of the tenth and the eleventh AND element connected to the output of the third OR element, the second input of which is connected to the output of the fifteenth And element, and in the device inverse and direct outputs of the first trigger of each category are connected, respectively, with the first inputs of the fourth and fifth elements AND of the neighboring low order, the inverse and direct outputs of the fourth trigger of each category are connected respectively with the first inputs of the ninth and twelfth elements of And the next low order, the first inputs of the fifteenth elements And of all bits are the information input of the device, the first, second, third, fourth, fifth, sixth and seventh clock inputs of which are connected respectively to the second inputs of the first and second AND elements, the second inputs and the third and sixth elements And, the second inputs of the fourth and fifth elements And, 10 the second inputs of the ninth and twelfth elements And, the second inputs of the thirteenth and. fourteenth elements And, with the second input of the fifteenth element And and with the first input of the seventh 15th element And of each category, characterized in that, in order to improve performance, each digit contains the seventh OR element and the NOT element, and in each 20 digit the second input of the fifteenth element. And through the element is NOT connected to the second input of the eighth element AND, the spot output of the twelfth AND element is connected to the third input of the second OR element ²⁵ and to the first input of the seventh OR element, the second input of which. connected to the direct output of the second trigger, the output of the fourth and seventh elements OR connected respectively to the first and second inputs of the sixteenth element And, and in the device the output of the sixteenth element And of each category is connected to the second input of the fourth element OR and to the 35 second input of the seventh element And the neighboring high-order bit, the output of the tenth element AND of each bit is connected to the third input of the fourth 'element · OR the neighboring high-order. 40 rows. Forwarding code from TRZ 8 TrCh (first) Addition of codes modulo 2 (first) Formation of transfer potential Forwarding code from Tr. 3 6 Tr. 4 (second Addition of codes modulo 2 (second) Figure 2