SU1236614A1 - Digital-frequency integrator - Google Patents

Abstract

The invention relates to automation and computing and can be used to integrate the value given by varying: in time, the pulse frequency i. The aim of the invention is h-1 to increase accuracy by reducing the integration error of the input pulse sequence. The increment of the pulse sequence at the output of the generator 3 reference pulses causes a corresponding increment of the pulse sequences at the output of the binary multiplier 2 controlled by the first counter 4 frequencies and at the output of the And 7 element, from where these sequences go to the counters 5 and 6 pulses, respectively. The outputs of all bits of the counters 5 and 6, except the younger ones, are connected respectively to the inputs of the adder 8, the output of which generates a code corresponding to the time integral from the input pulse sequence received via the input bus 1 to the input of the counter 4 pulses. 1 il. with S (L Kvd SA Odd Ji 9

Description

t1

The invention relates to automation and computer technology and can be used to determine the time integral of a value specified in the form of a pulse frequency varying with time.

The purpose of the invention is to increase accuracy by reducing the error of integration of the input pulse sequence. .

The drawing shows a structural electrical circuit of the device.

The digital frequency integrator contains an input bus 1, a binary multiplier 2 frequencies, a generator 3 reference pulses, the first 4, second 5 and third 6 pulse counters, element 7, adder 8, output buses 9.

In the digital frequency integrator, the output of the generator 3 is connected to the frequency input of the binary multiplier 2 frequency, the output of which is connected to the input of the second counter 5, input

s

  % a. ,, + a 2 +. . .a, 2 °). ,,

c - -; (one}

„1t, - 1

where ha is the counter size 4; a is a significant i-ro (i

152, .. ,, m-l) of a digit in counter 4, taking the value O or 1. The increment dN of the pulse sequence N at the output of the element And 7, caused by the increment of the pulse sequence N, is described by the expression

, ,, a, (2) where a is the most significant digit in counter 4,

h 2: + fiNoIa i.2lLi2tt 2.2i; l ± ia 2: i

Finally

, m - A,

(five)

or

M.

N,

(6)

-.t-7

 2 Vn

binary number in the counter 4;

- number of impulses of impulses -

Noah sequence from the output of the generator 3;

4 j

bus 1 is the input of the first counter 4, the output of the higher bit of which is connected to the first input of the element And 7, the second input of which is connected to the output of the generator 3. The outputs ml; the lower bits of the first counter 4 connect to the corresponding control inputs of the binary frequency multiplier 2, the output of the And 7 element is connected to the input of the third counter 6, the outputs of all but the lower bits of the counters 6 and 5 are connected to the corresponding first and second inputs of the adder 8, the outputs of which are the output buses 9.

The digital frequency integrator works as follows.

The increment oi 11 of the pulse sequence NJ ,, at the output of the generator 3 causes the output of the binary multiplier 2 to increment cJ N of its output pulse sequence N, and

thirty

Immediate value (11 ff

The pulse N and N sequences are fed to counters 5 and 6, respectively. Considering that the floating bits of these counters are not connected to the inputs of the adder, they write an expression that determines the increment about the M value of the M code at the output of the adder, caused by the increments cN and cvLNj pulse sequences N and Nj at the inputs of counters 5 and 6. o / M + N,; (3)

(four)

M - the code value at the output of the adder 8.

Expressions (5) and (6) are similarly expressed: and m, describing the operation of the binary frequency multiplier used in the known device with a counter-divider counter.

When a pulse sequence Np (t) 5 is fed to the input bus of a pyrfrequency integrator, which is a function of time, the current value of the number (t) is generated in the counter. Considering that

Xh

  f, (7)

where f is the pulse frequency at the output of the generator 3, an expression is obtained for incrementing the code value at the output of the adder 8

“. (eight)

Hence the current value of the code M at the output of the adder 8 is equal to

t

“. f .- | j ,,

M

(9)

or by designating

K -2L TP1

 TO

I

Bh

(t) t

(YU)

Thus, at the output of the adder 8 a time integral is formed from the input pulse sequence Ng (t).

j. Improving the accuracy of the proposed

the digital frequency integrator in comparison with the limestone is achieved by reducing the integration error during the reproduction of the dependence (6).

Editor E. Papp

Compiled by V.Voytov Tehred I.Popovich Proofreader V.Sinitska

Order 3098/58 Circulation 816 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d, 4/5

Production and printing company, Uzhgorod, Projecto st., 4

12366144

Claims (1)

Invention Formula five YU 15 20 five 0 A digital frequency integrator containing a binary frequency multiplier, first and second pulse counters, a reference pulse generator, the output of which is connected to the frequency input of a binary frequency multiplier, the output of which is connected to the input of the second pulse counter, and the control inputs to the corresponding lower-order outputs of the first counter impulses, the input of which is an input bus, which is different to and with the fact that, in order to improve the accuracy, a third impulse counter, an adder and an And element, whose first input It is connected with the output of the higher bit of the first pulse counter, the second input is with the output of the reference pulse generator, and the output is connected with the input of the third pulse counter, the outputs of all bits of which, except the younger, are connected to the corresponding first inputs of the adder, the second inputs of which are respectively connected with the outputs of all but the younger, bits of the second pulse counter, and the outputs are the output buses.