SU1236558A1 - Device for checking memory - Google Patents

Abstract

The invention relates to computing and can be used to control semiconductor operational and persistent storage devices. The aim of the invention is to expand the functionality by controlling the blocks of RAM and fixed memory and increase the reliability of the device. The device for memory control registers address 1, 2, 6, switches 3, 18, microprogram control block 13, data generation blocks 5 and write and read pulses 9, number register 10, blocks 11, 14., 15 comparisons, block 12 stopping unit, frequency setting unit 10, modulo-two control unit 20, shift registers 21, initial 22 and final 23 addresses, commands 24 and control results 25, block 26. Before starting the operation, the control computer loads registers 21-25 through the interface 26. On command from register 24, a firmware control unit 13 is started, which generates a control test. When an error is detected by the comparison unit 11, an interrupt signal is generated. The device provides a self-monitoring mode by issuing test stimuli from the outputs of the switch 18 to the information inputs of the device. The proposed device provides the ability to control the process control using a computer. 7 il. $ (L y with O5 ate O1 00

Description

The invention relates to computing and can be used to control semiconductor operational and persistent storage devices.

The purpose of the invention is to expand the functionality by controlling the blocks of operational and permanent memory and increase the reliability of the device.

FIG. 1 shows a diagram of the proposed device; in fig. 2 is a control block diagram; in fig. 3 is a diagram of a data generating unit; in fig. 4 is a diagram of a write and read pulse generation unit; in fig. 5 is a block circuit diagram; in fig. 6 is a diagram of a firmware control block; in fig. 7 is a block diagram for setting frequencies.

The memory monitoring device contains (FIG. 1) the first 1 and second 2 address registers, the first switch 3, the control unit 4, the data generating unit 5, the third address register 6, the first element And 7, the trigger 8, the pulse shaping unit 9 write and read, register 10, the first block And the comparison, the block 12 stop, the block 13 of the firmware, the second 14 and the third 15 blocks of the comparison, the second 16 and the third 17 And elements, the second switch 18, the frequency setting unit 19, the control unit 20 modulo two, shifted, st register 21, registers of the starting address 22, finite address 23, commands 24, control results 25, interface block 26, first device input 27, for receiving monitored data, second device input 28, for exchanging information with a control computer or control panel, third device input 29, for receiving reference data, the fourth device input 30, for receiving an external trigger signal when the device is operated as part of other control devices or systems, fifth device input 31, for receiving external signals the clock frequency, the first output 32 of the device intended for issuing read and write signals to the memory blocks, the second output 33 of the device intended for issuing an address to the monitored memory, the third output 34 of the device intended for issuing data to the monitored memory the fourth 35 and fifth 36 outputs of the device, intended, respectively, for issuing signals about the presence of a malfunction and the beginning of a new control cycle and used when the device is operated as part of other devices and control systems.

The control unit 4 contains (FIG. 2) a counter 37, a decoder 38 shifting the register 39, the first 40, the second 41, the third 42, the fourth 43 and the fifth 44 switches.

The data generating unit 5 contains (FIG. 3) the input 29 of the reference data, the output 34 of the control data, the first 45 and second 46 data registers, the first 47, the second 48 and

the third 49 switches, the third 50 and the block 51 amplifiers.

The writing and reading pulse shaping unit 9 contains (FIG. 4) the first 52 and second 53 And elements, the first 54 and the second 55 amplifiers, the trigger 56.

Stop unit 12 contains (Fig. 5) input 30 for external triggering, output 35 for a fault signal, output 36 for a signal about the start of a new monitoring cycle, trigger 57, 0 first 58, second 59 and third 60 elements OR, first 61, second 62, third 63 and fourth 64 elements I.

The firmware control unit 13 contains (FIG. 6) the address counter 65, the permanent memory unit 66 (made, for example, on the basis of the 556PT7 chip), the decoder 67, the control trigger register 68, the trigger 69, the control unit 70 modulo two, the first 71, the second 72, the third 73 and the fourth 74 elements I.

0 The frequency setting block 19 contains (FIG. 7) an external clock frequency input 31, a clock frequency generator 75, a first 76 and a second 77 AND elements, an OR 78 element, a counter 79, and a switch 80.

The device works as follows. 5Before starting operation, the corresponding inputs / outputs of the device are switched to the outputs / inputs of the monitored memory block. Then the control computer starts the execution of the control program. To do this, the device receives the following information via the interface block 26: register 22 - the starting address of the monitored memory array, register 23 - the final address of the monitored array, the registers 45 and 46 of the data generation unit - the initial check codes, the register 24 is a command code defining the operation mode of the device during memory monitoring (type of test being performed, monitoring operating frequency, cyclic or single monitoring mode). The team goes to the device last. The recording signal, fixing its reception to the register 24, is transmitted from thereafter to the stop unit 12. The latter sets "1 flip-flop 57, which supplies the operating frequency through AND 64 to the device, and enters the microprogram control unit 13. In this block, this signal receives the assigned test code from the register of 24 commands to the address counter 65 and includes the frequency from the output of the AND 73 element as a “- | -1 signal to the contents of the address counter and to the polling of the decoder 67. From this moment begins run firmware.

From a block of permanent memory, codes are selected that correspond to the assigned micro j program, which depends on the type of monitoring test assigned. These codes are sent to the decimator 67, the signals from which are set in the appropriate position

five

0

register triggers 68. The control potentials of these triggers arrive at the device blocks and prepare the execution of the assigned control mode. At the end of the firmware execution, the frequency entering into the counter 65 and the decimator 67 is turned off by setting the flip-flop 69 to "O" and includes the frequency received, and from the output of the AND 72 element to the control unit 4. By this action, control from block 13 is transferred to block 4, which controls the assigned control mode.

The execution of the microprogram is followed by the monitoring of modulo-two codes selected from the permanent memory by means of block 70. If the malfunction is not fixed during the program, then the control mode is executed. In the same case, when the fault is detected and the signal about this from the output of the element 71 enters the register 25, the interface unit 26 provides for outputting an interrupt signal to the computer. A subroutine repeating the assignment of the monitoring mode is provided on this signal. If a fault is also recorded during the repetition, the computer informs the operator of this.

When the control is transferred to block 4, the mode starts to be executed in accordance with the timing diagram implemented by the counter 37 and the decoder 38. The signals from this descrambler arrive at the switch 40, where they are switched according to the assigned mode using the potentials coming from the block 13 and, during performing control with signals from blocks 14 and 15 of the comparison. The signal from block 14 pre-passes selection using the shift register 39 and switch 41. The selection is caused by different numbers of check cycles of a given memory array in various control tests.

The addresses of the monitored memory cells in the test code are generated using the first 1, second 2 and third 6 address registers. The size of the first register is determined by the number of rows (t), and the size of the second register by the number of columns (n) of the matrix being checked. The capacity of the third register is equal to the size of the checked memory block (P). Between these values there is a ratio P. The comparison unit 12 in the device serves precisely to fix the moment of equality for the given relation. In addition, when registers 1 and 2 are filled synchronously, this block records the time when register 6 registers the address of the diagonal of the monitored memory matrix. Comparison unit 14 fixes the moment of equality of the current and final addresses. With the help of the element And 17 is achieved the definition of the moment of equality of the current, base and end addresses, which occurs at the end of testing a given array. Elements 7 and 16 are intended for the corresponding switching of address registers when performing tests with different variants of address search. The issuance of a specific address to the monitored memory takes place via switch 3, controlled by trigger 8.

The formation of control data takes place in block 5 with the help of registers 45 and 46, information in which is initially received from a computer. Information

0 in these registers is affected by the shift pulses from control unit 4. Switches 47 and 48 are included in the transfer chains of these registers. They allow the formation of registers in addition to simple codes ("O -.-. O,

 “11, the shahmat code, running“ 1, running “O, etc.) pseudo-random sequences. The control code in block 5 is generated both by the indicated changes in the registers and by the possibility of connecting to the output of the block using the switch 49 of one register or the other. The switches 47 and 48 are controlled by the firmware control unit 13, the switch 49 is controlled by both the unit 13 and the control unit 4, which switches the trigger 50, the output of which is connected to the control input of the switch. In addition, information coming from the reference block (input 29) can be connected to the output of the block. This is used when monitoring the blocks of the fixed memory using the reference

° compare. The generated code is issued to a monitored memory from output 3 via amplifiers 51.

The formation of the write and read pulses occurs in block 9. The write and read pulses appear at the outputs of the AND elements 52

 and 53. The condition for their occurrence is the absence of blocking from block 13, the corresponding state of trigger 56 and the presence of a survey of elements 52 and 53 from block 4 of control. The write and read pulses enter controllable memory blocks through amplifiers 54 and 55.

In the process of control, the information previously recorded in the monitored blocks is read out and through input 27 enters

 register 10 numbers. From the output of this register, the data enters the comparison unit 11 and the control unit 20 modulo two. In block 11 there is a comparison of control data from block 5, and data

Q received from controlled memory. In block 20, the monitored information is modulo-two checked (for example, by monitoring the read-only memory). If the failure of these blocks is not fixed, the device continues to work on the implementation of the established control mode. The end of the work in this mode is recorded by the appearance of the signal at the output of the element And 17. This happens when comparing the addresses in blocks 14 and

15. This signal enters the block 12 stop. In the absence of a lock of the cyclic execution of the control, the OK enters from the output of the element AND 61 to the register 25 of the results of the control and then to block 26, which organizes the interruption of the computer. According to the interruption of the computer, the execution of the following control test is assigned in the described manner, the execution of fiOTOporo is determined by a congrol program. The end of the control program is fixed by the computer. which also informs the operator about this.

In the event of malfunctioning in blocks 1 1 or 20, a corresponding signal is generated. These signals also come in block 12 and, in the absence of an interlocking fault, stop the operation of the device by setting it to “On trigger 57 (through the OR element 59), blocking the arrival of frequency into the device, go to register 25. Next comes the interruption of the computer that goes to the required subpro1– the frame (subprogram is determined by the interrupt code, cq) is opted in register 2o).

The subroutine is executed on the basis of the married algo) and can be obtained. Additional data for analyzing the control: count the data from block 5, the monitored data from register 10 and the address of the malfunction from the switch 3. In order to clarify the nature of the malfunction and program localization, the necessary control tests can be assigned. All information about the results of the control is issued to the operator with a non-peripheral equipment connected to the EV / L.

The operating frequency of the control is set in block 19 room. This is determined by the code received in command source 24, which controls the switch 80, connects the corresponding output 1 of the counter 79. The frequency of this counter can come from either the internal 75. or the clock generator.

In addition to performing control tests, the device provides self-checking tests. For this, the computer assigns tests that check the generation of information entering the controlled variable: address, data, write and read signals. For this purpose, a switch 18 and a cd are entered into the device, register 21. When checking the operation of the address formation schemes and computer data, sets the same laws for changing them and connects output 33 (address) from iiorvio- 11 {switch 18 to data input 27 Then, the comparison mode is launched with the data generated by block 5. The operability of the tested parts of the device is fixed in the same way as when determining the performance of the monitored memory.

When checking the signal output, the record is: -; and reading work happens the following way, in the image.

The computer assigns the execution of a single cycle, such as recording. The time of occurrence of the recording signal is fixed on the shift register 21 by the position code by supplying the shift pulses from block 13 to it at a certain time. Next, this code is switched by switch 18 with input 27, and then pa 11 compares this code with a predetermined code that is transmitted from the computer to the block registers

5, the right of outputting a reading signal is also determined in a similar way.

Claims (1)

Invention Formula A memory control unit containing a microprogram control unit, the first and second outputs of which are connected respectively to one input of the write and read pulse generation unit and to the first input of the first And element, the outputs of the first and second groups of the microcircuit.viHoro control unit are connected to the inputs of the first goopp of the data generating unit and the control unit; the outputs of the first, second, third, fourth and fifth groups of which are connected respectively to the information inputs of the first, second and third registers address a, with other inputs of the write and read pulse shaping unit and with input ;;, the second group of the block (data fixing, first block output;. Gg -;.; 1 input connected to the trigger input, and the second output connected to the first block input stop, the second input of which is the input of the external start-up of the device, the third input of the sub-section: 1 is connected to the output of the first comparison unit, the outputs of the first group are connected to the inputs of the first group of the firmware control unit, and the first and second outputs are respectively the output - gi and cycle start device, the trigger output is connected to the control input of the first switch, the information inputs of the nerve, the second and third groups of which are connected respectively to the outputs of the first, irroporo and third address registers, and the outputs are address outputs of the device, the inputs of the first group of the first block are 1G: ; 11I are connected to the outlet, the first group of the forming unit, the outputs of the second group of which are the information outputs of the device, and the inputs of the third group are the second information inputs of the device, inputs v The first group of the first I block of comparison is connected to the outputs of the re- | The number source, the KOTOpoi inputs are the first information inputs of the device, the output voltage of the write and read pulses is the output of the write-read of the device, the control output of the first register of the A.cres is connected to the second input of the first And element, the output of which is connected to u: select the input of the second address register, characterized in that, in order to increase the reliability of the device, the second and third comparison blocks are introduced into it, the second and third AND elements, the second switch, the frequency setting unit, the control unit modulo two shift register, registers of start and end addresses, command register, control results register and interface block, the inputs of the first group of the interface block are connected to the outputs of the number register and the inputs of the control module modulo two, the output of which is connected to the fourth input of the stop block, the inputs of the second group of the interface unit are connected to the inputs of the first group of the second comparison unit and the second switch and with the outputs of the first switch, and the inputs of the third and fourth groups are connected to the outputs of the results register The ol and the outputs of the first group of the data generating unit, respectively, the outputs of the interface block are connected to the inputs of the end and start address registers, the command register and the inputs of the fourth group of the data forming unit, and the bidirectional inputs (outputs are inputs) are connected to the device interface outputs , the outputs of the end address register are connected to the inputs of the second group of the second comparison unit, the output of which is connected to the first input of the control unit and to the first input of the third element I, the second input of which is connected to third course to 8 omi4 about t 22 k12 from 13 ipuz.Z 0 five 0 five the comparison unit and the second input of the control unit, and the output is connected to the fifth input of the stop unit, the outputs of the initial address register are connected to the inputs of the second group of the control unit, the outputs of the command register are connected to the inputs of the second group of the microprogram control unit, to the inputs of the first group of the stop unit and with the inputs of the frequency setting group, the input of which is the clock input of the device, and the output is connected to the sixth input of the stop unit, the outputs of the second group of which are connected to the information inputs of the register cut Controls, the control input of which is connected to the third output of the firmware control unit, the fourth output of which is connected to the first input of the second element And the outputs of the third and fourth groups are connected respectively to the inputs of the second group of the second switch and to the information inputs of the shift register, the output of the second element And it is connected to the control input of the third address register, and the second input is connected to the control output of the second address register, the inputs of the first, second and third groups of the third block cf vneny connected to outputs of the first, second and third address registers, respectively, the second switch outputs are connected to inputs of the first information device and a control input coupled to the output of the read-write device. Kb K5 K9ot151 from 13 to tt, z6 fig.z from 17 about t 20 5 Ki6 to from 24 to 25  n1v from 12 FIG. 6 / Kf2 about t 2 80 t 79 Compiled by O. Isaev Editor M. BlanarTehred I. VeresKorrektor A. Obruchar Order 3015/56 Circulation 543 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab. 4/5 Branch PPP "Patent, Uzhgorod, st. Project, 4 FIG. 7