SU749887A1 - Semiconductor memory control device - Google Patents

Description

DEVICE FOR CONTROL OF HALF-UTILITARY

(54) MEMORY

The invention relates to the field of storage devices. A device is known comprising a clock pulse generator connected to a test sequence generator and a unit analyzing the response of the test memory to test effects generated by the generator 1. The disadvantage of the device lies in the fact that it does not provide fault localization. The closest technical solution to this is a device for monitoring a semiconductor memory, comprising a clock generator, a test sequence generator, a control unit, a timing diagram forming unit, a level matching unit, a comparator, the clock pulse output connected to the test sequence generator and an input of a time diagram forming unit, the outputs of which are connected to the first inputs of the level matching unit, controlling the input of the generator clock pulses, a test sequence generator, and a time diagram generation unit are connected to one of the outputs of the unit, one of the inputs of which is connected to the outputs of the clock generator and the test sequence generator and the comparator output of which is connected to the input of the device 2. The disadvantages of this device are that it provides for the detection of defective storage cells, but does not determine the reasons for their malfunction, and also does not provide accurate fault localization, which limits the scope of this device. The purpose of the invention is to extend the field of application of devices for monitoring semiconductor memory by providing opportunities for conducting diagnostic tests. The goal is achieved by the fact that the device contains a code converter, an address multiplexer, a screwdriver, first and second drives, and the outputs of the test sequence generator are connected respectively to the input of the code converter and the first,

(; r. - -; d5I. INPUT of the address multiplexer, the second input of which is connected to the counter output, the outputs of the converter & code gate) are connected to the second inputs of the level matching unit and the control inputs of the comparator and the second accumulator, the outputs of the address multiplexer are connected to the address inputs accumulators and the third inputs of the level matching unit, the outputs of which are connected to the outputs of the device, the output of the comparator is connected to one of the inputs of the first storage device, the output of which is connected to one of the inputs of the control unit The driving inputs of the converter codes, the address multiplexer, the counter and the accumulators are connected to other outputs of the control unit. The drawing shows a block diagram of the proposed device. The device contains a clock generator, a generator 2 of test pattern, a control block 4, a timing diagram forming unit 4 , a unit for matching the level 5, a comparator 6, the input 7 of which is the device input, a code converter 8, an address multiplexer 9, a counter 10, the first 11 and the second 12 drives. The device is connected to the semiconductor memory unit 13. The output of the generator 1 clock pulses is connected to the input of the generator 2 of the test sequence and the input of the time diagram forming unit 4, the outputs connected to the first inputs of the level matching unit 5. The control inputs of the generator 1, generator 2 and unit 4 are connected to one of the outputs of control unit 3 whose inputs are connected to the output of generator 1 and 2, to the outputs of comparator 6 and the output of accumulator 11. The outputs of generator 2 of the test sequence are connected to the corresponding input of converter 8 codes and the first input of the address multiplexer 9. The transducer outputs 8 codes are connected to the second inputs of the level matching unit 5 by the supervisory inputs of the comparator 6 and the storage device 12, and the outputs of the multiplexer 9 are connected to the address the inputs of the drives 11 and 12 and to the third inputs of the block 5, the outputs of which are connected to the outputs of the device. The input 7 of the comparator 6 is the input of the device and is connected to the output of the control unit of the memory block 13, and the output of the comparator 6 is connected to one of the inputs of the accumulator 11. The control inputs of the converter 8 of the code, the counter of the multiplexer 9, the counter 10, the accumulators 11 and 12 are connected to other outputs of the control unit 3. The output of the pin 10 is connected to the second input of the address multiplexer. 9.

749B87 The device operates as follows. At the beginning of the test, control unit 3 receives the setup signal to the initial state of the generator 2 of the test sequence and counter 10, and the first drive 11 is filled with zeros. Then, 1 clock pulse generator is started. Generator 2 test sequence under the action of so. The pulse from generator 1 begins to generate a sequence of test actions from the original test sequence, which consist of control signals and address signals. Control signals without conversion are transmitted via a converter. 8 codes to the inputs of the level matching unit 5. The addressing signals are transmitted to block 5 via address multiplexer 9. Block 5, in accordance with the time sweep signals generated by block 4 under the action of clock pulses from generator 1, transmits control signals and addressing signals to the inputs of the tested semiconductor memory. If the actual test action is a read operation, comparator 6 compares the response value of the monitored memory block with the desired response. If a mismatch is detected, a signal 1 appears at the output of the comparator 6, which is fed to the information input of the accumulator 11 and to the control unit 3, which prohibits the operation of generator 1, detects the inconsistency and generates a write pulse to the accumulator 11 at the address of the failed memory cell fixing her address. At the same time, unit 3 forms a recovery cycle for a failed memory location. In this case, the converter of 8 codes under the action of signals from block 3 converts control signals that at this time represent a read operation into signals corresponding to a write operation of F or 1, depending on what type of desired response the converter of 8 codes is currently generating. Unit 4, under the action of a pulse from control unit 3, forms the next timebase cycle, in accordance with which unit 5 transmits a new value of control signals to the inputs of the tested semiconductor memory unit. Addressing signals are not changed. After the block 3, the control enables the generator 1, which starts the generator 2, generating a queued test action, and the process repeats until the end of the initial test sequence, at the end of which the generator 2 digs out the corresponding signal, which goes to the control block 3. Block 3 in this case, it prohibits the operation of Generator 1 and checks the condition: if there was at least one failure when testing for the original test after DOWNLINK If there were no failures, it is concluded that ytuemogo semiconductor memory unit. If at least one occurred, which is fixed in block 3 of the control, go to the diagnostic stage, which begins with a survey of the drive P to find the address of the first failed cell. For this, the control unit 3 sequentially changes the state of the counter 10, from which output the CABC signals of the Air & M multiply barb 9 to the address inputs of the accumulator 11. With each change in the state of the Pbd counter, the signal from the control unit 3 reads the information from the memory cell drive II with the address corresponding to the state of the counter. 10. Block 3 each time analyzes the state at the output of accumulator 11 and, if the read information O is, its polling continues, and when reading 1, the polling stops. Counter 10 records the value of the bad memory cell. Then the control unit 3 for determining the operability of this memory cell generates a sequence of five pulses, which are fed to the input of the time diagram forming unit 4 and the input of the converter 8, which, in accordance with these pulses, sequentially generates signals corresponding to the operations: write O, write 1, read 1, write O and read O. The address multiplexer 9 continues to transmit the value of the address from the outputs of counter 10. If a mismatch is detected by the comparator 6, block 3 forms recording pulses in the second accumulator 12 value analyzing test exposure, in which a mismatch was found, and the value of the prior analysis of the test exposure. Then unit 3 resumes polling the first accumulator 11. If no match was found for the required response, control unit 3 generates a write signal O to the first accumulator 11 at the address corresponding to the counter 10. The test for the spurious test cell sequence begins whose address is fixed by the counter 10. Test mode for the expanded test sequence differs from test mode to the initial one in that the control unit 3 sets the test generator 2 tigators NOSTA on mode, in which it generates the next test action on each odd clock pulse generator with nocTynaidschemu I. Test commences with the launch clock pulse generator I. Under the action of the first clock iMpute generator 2 produces the first test effect. The address multiplexer 9 transmits to its output the addressing signals from the generator 2 output, under the action of the control signal, from the generator 2, the clock 4 from the generator 1 generates a time base, under the action of which the block 5 transmits a test action to the inputs of the memory block under test. Then, under the action of the second clock pulse from the oscillator A, the control unit 3 switches the address multiplexer 9 to transmit signals from the output of the counter 10. At the same time, under the influence of the signals from the control unit 3, the code converter 8 converts the control. the part of the test action coming from the outputs of tori 2 torus to the new test action corresponding to the operation of ssytygvani, and block 4 under the action of the clock pulse from generator 1 forms the next cycle of time base, under the action of which unit 5 transmits the test action from the outputs of the code converter 8 and address multiplexer 9 to the memory block under test. The generator 2 at the same time continues to give the last test effect. The comparator compares the value of the reaction of the monitored memory block with the required one, which is generated by the code converter 8 under the action of signals from the control unit 3. If an inconsistency is found, unit 3 prohibits the operation of generator 1, forms a recording impulse, and Eapissy's tutorial 12, the value of the test action that was currently applied to the test memory block. Then, the converter 8 and the address multiplexer 9, under the action of the signal from block 3, start transmitting to their outputs the value of the TesA value in the influence generated by generator 2. The value of this Test Effect under the influence of the write pulse from block 3 is recorded by accumulator 12. After that, block 3 forms a recovery cycle the bad memory cell, after which it resolves the operation of generator 1. If the test sequence generated by generator 2 is not completed, it begins to generate the next test action, and The above test sequence for the test sequence is repeated until its completion. After the end of the test sequence, unit 3 resumes polling the accumulator 11, and when 1 is checked, the next failing memory cell is checked for performance, and then with a positive outcome of such a test, the test for the cleared test sequence dp of the given memory cell begins. This process is repeated until the polling of the drive 1I is completed. After the test, the addresses 11 of the memory cells inoperative were fixed, and the drive 12 recorded the test results by which the defective tees can be identified. The technical and economic advantages of the described device are that it provides high accuracy and accuracy of the lock, malfunctions in the semiconductor memory blocks, including the localization of multiple errors, obtaining diagnostic information in the form that does not require complicated computations, and also allows can not be used to diagnose malfunctions of the memory npocTbie test sequences and significantly reduce the time of localization of malfunctions without operator intervention in the control process, applied Moreover, the described device allows one to fully automate the control of semiconductor memory blocks and to use diagnostic information to adjust the technological process of manufacturing semiconductor memory in order to increase its reliability, which significantly expands the field of application of devices. Formulas of the invention. A device for controlling a semiconductor memory, containing a clock pulse generator, a test sequence generator, a control block, a time diagram generation unit, a level matching unit, a comparator, the clock pulse generator output connected to the test sequence generator 1 to the input of the time diagram forming unit, the outputs of which 7a are connected to the first inputs of the level matching unit, the control inputs of the clock generator, the dough generator th sequence forming block and timing diagram. connected to one of the outputs of the control unit, the inputs from the inputs of which are connected to the outputs of the clock generator and test sequence generator and the output of the comparator, whose input is connected to the device input, characterized in that, in order to expand the field of application of the device by providing conducting diagnostic tests, it contains a code converter, an address multiplexer, a counter first and a second drive, and the outputs of the test sequence generator are connected Here, respectively, to the input of the code converter and the first input of the address multiplexer, the second input of which is connected to the counter output, the outputs of the code converter are connected to the second inputs of the level matching unit and the control inputs of the comparator and the second accumulator, the outputs of the address multiplexer are connected to the address inputs of the drives and the third inputs block matching levels, the outputs of which are connected to the outputs of the devices, the output of the comparator is connected to one of the inputs of the first drive, the output of which is With one of the inputs of the control unit, the control inputs of the code converter, the address multiplexer, the counter and the accumulators are connected to the other outputs of the control unit. Sources of information taken into account in the examination 1. US Patent G 3719929, cl. 340-146, 1, 1974. 2. US patent number 3806243, cl. 340-146.1, 1974 (prototype).

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Claims (1)

Claim A device for monitoring a semiconductor memory, comprising a clock generator, a test sequence generator, a control unit, a time chart generation unit, a level matching unit, a comparator, the output of the clock generator being connected to the input of the test sequence generator and the input of the time chart generation unit, the outputs of which connected to the first inputs of the block matching levels, the control inputs of the clock generator, test generator subsequently ^: spine and block forming the time diagram. connected to one of the outputs of the control unit, one of the inputs of which are connected to the outputs of the clock pulse generator and the test sequence generator and the output of the comparator, input _{] 0 of} which is connected to the input of the device, characterized in that, in order to expand the scope of the device due to the possibility of diagnostic tests, it contains ₁₅ zovatel transformation code, the address multiplexer counter * first and second drives, wherein the outputs of the test sequence generator is connected respectively, to the input of the code converter and the first input of the address 20 multiplexer, the second input of which is connected to the counter output, the outputs of the code converter are connected to the second inputs of the level matching unit and the control inputs of the comparator and the second drive, the outputs of the address multiplexer are connected to the address inputs of the drives and the third the inputs of the level matching unit, the outputs of which are connected to the outputs of the devices, the output of the comparator is connected to ₃₀ one of the inputs of the first drive, the output of which is It is connected to one of the inputs of the control unit, the control inputs of the code converter, address multiplexer, counter and drives are connected to other outputs of the control unit.