SU1234831A1 - Device for extracting square root - Google Patents

Abstract

This invention relates to the field of computing. The purpose of the invention is to increase speed. The device operates in a number system with a natural base. The square root extraction cycle consists of M cycles. In each measure, one P-digit root is determined. To determine it, the P-1 differences of the previous remainder and the increment of the radicand with each of the angles obtained for the used number system are simultaneously calculated. From the signs of the calculated differences, the next 1C1Fra square root and the next residue are determined. 3 ep f-ly, 6 ill.

Description

The invention relates to computing and is intended to extract the square root of the numbers represented in the binary-decimal system.

The purpose of the invention is to increase speed.

Fig. 1 shows a block diagram of a device for extracting a square root; in fig. 2 is a diagram of the summation block; in fig. 3 - diagram of the correction unit; in fig. 4 — block diagrams of bitwise additions; in fig. 5 - encoder scheme; figure 6 - scheme of a two-channel switch.

The device (Fig. 1) contains a register 1 root, a register 2 radixes, M-1 decoders 3.1, 3.2, ..., 3, M-1, block 4 of bit addition, block 5 correction, block 6 forming multiples, nine There are 7.1-7.9 summation blocks, a two-channel switch 8, an encoder 9, the first 10 and the second 11 registers.

The summation unit 7 (Fig. 2) contains M one-bit binary-decimal adders 12.1, ..., 12.i ... a leading transfer unit 13, the bus 14 of the logical zero of the device.

Block 5 correction (Fig. 3) contains the element 14.1-l4.M-2 IL, element IPI-NOT 15, the element And 16 n trigger 17.

Block 4 of the bit addition (Fig. 4) contains the first 18 and second 19 groups of elements NOT, the first 20 and second 21 binary adders, the first 22 and second 23 groups of elements And the ngin 24 of the binary 10 of the device.

The encoder 9 (Fig. 5) contains the elements NOT 25-33, the elements And 34-41, the elements RSHI 42-45.

Two-channel switch 8 (FIG. 6) contains nine elements NOT 46-54, eight elements AND 55-62, two groups of elements 10 AND-OR63 and 64

Consider the operation of the device.

The positive expression is positive (), is represented in binary-decimal notation and contains M bits without taking into account the sign bit. In one cycle, one binary-decimal digit of the M-bit square ROOT is determined, which is obtained by c:;

At the same time, nine positive angles are calculated, where each angle is the double product of all previously obtained

R-ICNY: square-root numbers on

corresponding to this corner is a digital factor of a number of 1, 2, ..., 9 taking into account the weights plus the product of the number-factor to itself, taking into account the weight.

At the same time, nine differences of the type B1 V1-VO are determined; B2 U2-VO ... B (P-1) V (P-1) -BO, where (VO) is the next shifted negative balance of the previous measure, plus the increment

N, U1, U2, ..., Y (P-1) are the corresponding positive angles.

Signs of the resulting differences B1, B2, ..., B9 are determined.

A real negative is selected.

the remainder of this cycle is determined by the signs of the obtained differences B1, B25 ..., B9, and the next binary-decimal square root is determined.

The resulting real negative balance is shifted by two bits to the left, writing to the two lower bits of the increment of the radicand.

In the next clock cycles, the operations of the considered algorithm are repeated, but the number of bits in the corners increases with each clock cycle. A diagram describing the acquisition of angles and the process of square root extraction are given. Let the square root value, 658, then fflxffl -N 0.432964 be the exact value of the radicand. Round this value to three digits, 433.

The diagram at the top shows the formation of angles from the square root figures obtained in the previous bars, and only the angles are shown, the summation of which with a negative

the remainder of the preceding measure gives the real negative. the rest of this measure. The bottom of the diagram shows the square root extraction process.

The first beat of the numerical expression N is recorded in register 2 (Fig. 1), at the same time register 1 is cleared, register 10 and T1 igger 17 of block 5 is zeroed, and in each binary decimal register 11, nine digits are recorded.

Two older, meaningful bits of the radicand are supplied to the inputs of block 4, in which they are formed

addition to the highest digit of the number system used, i.e. up to 9. The resulting additions from the outputs of block 4 are fed to the inputs of the two lower bits of the summation blocks. To the similar inputs of the remaining bits of the summation blocks with

Weight O -1 -2

O, 6 5 O, 6 5 O

3 6 3

3 angle

.

N N

Oh 4

Oh 4

Numbers of bits M 6

1 cycle

LTD

1 corner

2 tact

9 O 9 O O

About About 9 8 1

2 angle

23A8314

the outputs of registers 10 and 11 are given the numbers O and 9, respectively, to obtain an additional code of negative increment N.

five

In the following measures additional

the code is obtained automatically.

ABOUT

25

ABOUT

4 8

4 o

6 4 4 About 4 8

2964 3

2 1

5 6 О О

- increment N

3

at

one

6

2

6 9 - increment and shift / 1 / ol. edishche

3 o

2

3 o

3 tact

9 O 9 O

Oh oh

8 8

3 angle

9 o

in each clock cycle, to the next two least significant bits shifted by two binary-decimal bits to the left, the increment value N is written, which means that in the beat when submitting the lower digit N to the younger digit it is necessary to submit an additional one, and in that digit which is the least significant bit if all the other bits on the right are zero. An additional unit is generated by correction block 5 (Fig. 3). In register 2, with each clock cycle, the subfloor shift is shifted two binary-decimal places to the left, zeros are written to register 2 on the right. All bits 2, except the older ones, are written to register 2. In the cycle in which all zeroes are at the inputs of the correction block, a correction unit appears at its output, which is fed into the lower bits of the summation blocks. A trigger 17 (Fig. 3) is included in the unit that is fed to the blocking input of block A (Fig. 4), thereby blocking its outputs. After the first clock cycle in register 1, all zeros are written, so there are no groups of signals at the outputs of the decoders of the 3rd group. In the first cycle, in blocks 7.1, 7.2, ..., 7.9, in accordance with the diagram, the positive values of the angles of the first cycle 01, 04, ... 81 are summed with the values of

8 8

Oh oh

increment N and shift

ABOUT

6

ABOUT

SHZ-8

0

0

5 5

five

0

the two higher bit expressions presented as additions. The resulting sums in the form of two binary-decimal numbers of bitwise sums and transfers c. the outputs of blocks 7.1–7.9 are fed to the corresponding inputs of the two-channel switch 8. At the outputs of the transfer of the summation blocks, the values of the transmission advances are formed, which are fed to the inputs of the decoder 9 and to the control inputs of the two-channel switch 8, where they determine the next root number and the real remainder given tact The second clock register 1 registers the value of the number of the root with the output of the encoder 9. Registers 10 and 11 record the value of the real remainder of this clock cycle, the root expression in register 2 is shifted to the left by two binary decimal places. The value of the first digit of the root is fed from the first bit of register 1 to the inputs of the group decoder 3.1, and at its output corresponding to the digit appears a signal that flows through the corresponding bus to the corresponding input of the multiples forming unit 6.

At the corresponding inputs of the summation blocks, the values of the second corners are formed for each of the factor figures 1, 2, .-., 9. The corners obtained are summed or

one-bit binary-decimal adders corresponding to the given digits of the summation blocks with the previous remainder and increment of the radicand shifted to the left two digits. According to the obtained residues at the outputs of the summation blocks, leading transfers and residues in the form of two numbers are formed. By the values of the advanced p-translations, the root number on the encoder 9 and the real remainder of the second clock cycle on the outputs of the switch 8 are determined. In the next clock cycles, all actions are repeated by analogy with the first and second clock cycles until all digits of the square one are obtained.

Claims (4)

1. A device dp square root, containing the first and second registers, the register of the radicand and the register of the root, characterized in that, with . In order to increase speed, the device contains a group of (M-1) decoders, where M is the size of the argument, a block that forms multiples, nine summation blocks, an encoder, a two-channel switch, a random addition unit, and a correction bit, the outputs of the first and The second tetrad of the radic expression is connected respectively to the first and second information inputs of the block of the bit addition, the output of the i-th (where ..., M) tetrad register of the radic expression is connected to the (1-2) th information input of the correction block, the output b Okeer signal correction unit is connected to the input of block blockade by bit-wise complement first and second outputs of the bit-wise complement block are respectively connected to first and second , the information inputs of all the summation blocks and the first and second information inputs of the two-channel switch, the output of the pythonator is connected to the input of the first tetrad of the root register, the output of the jth gate (..., M-1) of the tetra of the root register is connected to the input of the j-ro the group decoder, the j-ro outputs of the group decoder are connected to the j-th information input of the formation unit multiples, the k-th output (where, ..., 9) of the unit ten 15 25 20 thirty 35 40 45 50 55 formation of multiples is connected to the third information input of the k-ro summation block, (k + 8) -fi output of the multiplier generation unit is connected to the fourth information input of the k-ro summation block, the third information input of the first summation block is connected to the bus of the logical zero of the device that are older ( M-1) tetrads of the fourth information input of the first summation block are connected to the outputs of the senior ones (M-1) —the notebook of the root register, the younger tetrad of the fourth information input of the first memory, while the summation is connected to the binary bus the unit 1, the transfer output (where 1 1, ..., 9) of the summation block is connected to the input of the encoder and the t-th control input of the two-channel switch, the first output of the t-ro summation block is connected to ((+ 2) the second information input of the two-channel switch, the second output of the f-ro summation unit is connected to the (+11) th information input of the two-channel switch, the output of the first register is connected to the fifth information inputs of all the summation blocks and to the twenty-first information input of the two-channel switch, out The second register is connected to the sixth information inputs of all the summation units and to the twenty-second information input of the two-channel switch, the output of the correction unit of the correction unit is connected to the seventh information inputs of all the summation blocks and to the twenty-third information input of the two-channel switch, the first output of the two-channel switch is connected to the information input the first register, and the second output - to the information input of the second register, and the unit of one bit addition contains the first and second groups of elements are NOT, the first and second binary adders, the first and second groups of elements AND, and the inputs of the elements NOT the first group are connected to the first group of inputs of the first binary adder, the outputs of the elements NOT the second group are connected to the first group of inputs of the second. the binary adder, the second groups of inputs of the first and second binary adders are connected to the bus of the binary number 10 of the device, the outputs of the first binary key adder to the first inputs of the AND elements of the first group, the outputs of the second binary adder are connected to the first inputs of the AND elements of the second group, the inputs the first group of elements is NOT the first information input of a block of one's complement, the inputs of the second group of elements are NOT the second information input of the block of a pore of the additional complement, the second inputs of the element Both the first and second groups are interconnected and are the blocking input of the block of a bit addition, the outputs of the first and second groups of the AND elements are respectively the first and second outputs of the block of the bit addition, the correction block contains a group of (M- 2) the elements OR, the element OR — NOT, the element and the trigger; moreover, the output of the (1-2) -th element of the TEMP group is connected to the (1-2) th input of the element OR — NOT the first input of the AND element and to the input of the trigger setup, the inputs (i-2) -ro of the OR element of the group are (-2) -th information The input of the correction unit, the inverse output of the trigger is connected to the second input of the AND element and is the output of the blocking signal of the correction unit, the output of the And element is the output of the correction unit of the correction unit. 2. The device according to claim 1, characterized in that the summation unit contains M one-digit binary decadal adders and an advanced transfer unit, wherein the transfer outputs of single-digit binary decadic adders are connected to the corresponding discharges of the first input of the advanced transfer unit and are the first output of the summation unit, the outputs of the sum of one-digit binary-decimal adders are connected to the corresponding bits of the second input of the advance transfer unit and are the second In the code of the summation block, the output of the advance transfer node is the transfer output of the summation block, the first input of the first one-digit binary decimal adder is the seventh information input of the block J j 0 5 o five C 0 5 summation, the second input of the first one-bit binary decimal adder is the first information input of the summation unit, the third input of the first one-digit binary decimal adder is the first tetrad of the fourth information input of the summation block, the fourth, fifth and sixth inputs of the first and The first and second inputs of the second one-digit bits of binary-decimal adders are connected to the bus of the logical zero of the device, the third input of the second one-digit binary-decimal adder, VL. The second information input of the cushioning unit, the fourth input of the second one-bit binary-decimal adder is the first notebook of the third information input of the summation block, the fifth and sixth inputs of the z-ro (..., M) one-bit binary-decimal adders are the z-th tetrad of the fourth information input of the summation unit, the third and fourth inputs of the i-one one-bit binary-decimal adder are the (1-1) th tetrad of the third input of the summation unit, the first information input of the i-gb single-bit dvoich the nite total adder is (1-2) th tetrad of the fifth information input of the summation unit, the second input of the i-one single-digit binary decimal adder is (1-1) th tetrad of the sixth information input block summation. 3. The device according to claim 1, characterized in that the encoder contains nine elements NOT, eight elements AND and four elements S1I, 1 output of the first, second, ..., eighth elements of the NOT encoder are connected to the first inputs of the first, second “Elements / AND encoder, output of the first element AND encoder is connected to the first input of the first element of TI pinfrarator, output of the second element AND encoder is connected to the first input of the second element OR encoder, the output of the third element AND pinfrarator is connected to the second inputs of the first and second elements OR encoder, the output of the fourth element AND the encoder is connected to the first input of the third element OR of the encoder. the output of the fifth element AND encoder is connected to the third input of the first and second inputs of the third element OR encoder, the output of the sixth element AND encoder is connected to the third inputs of the second and third elements OR encoder, the output of the seventh element AND encoder is connected to the fourth inputs of the first, second and third ele - cops OR encoder, the output of the eighth element AND the encoder is connected to the first input of the fourth element OR the encoder, the output of the ninth element of the NOT encoder is connected to the fifth input of the first and the second input is the fourth OR elements encoder, the input of the first encoder element is not the first input of the encoder, k-ro NO encoder input element is connected to. the second input of the (k-l) -ro element of the AND encoder and is the k-th input of the encoder, the outputs of the first, second, third and fourth OR elements of the encoder are the output of the encoder. 4. The device according to claim 1, characterized in that the two-channel switch contains nine NOT elements, eight AND elements and two groups of (4.M-8) AND 10 AND elements, with the outputs of the first, second, and. .., of the eighth element of the NOT two-scaled switch are connected to the first inputs of the first, second, ..., eighth elements of the AND of the two-channel switch, respectively; the first inputs of all elements 10 AND-OR of both groups are interconnected and connected to the input of the first element NOT a two-channel switch, output of the pth (where, ..., 8) element AND a two-channel r the switch is connected to (p + 1) -m inputs of all elements 10 I-W of both groups, the tenth inputs of all elements 10 AND-OR of both groups are connected to the output of the ninth element of the NOT two-channel switch, the t-th input of the n-th (where, ..., (4.M-8) of the element 10 I-IPI of the first group is the i-th binary bit of the (1 + 2) -th information the input is two-channel on the switch, the 1st input of the g-th element 10 AND-OR of the second group is the -th binary bit (t + 11) -ro of the information input of the two-channel switch, the twentieth input d-ro (... , (4.V-16) element 10 of the first group is the d-th binary bit of the twenty-first information input of the two-channel switch, the twentieth inputs (4.M-15) -th, (4.M-14) -th, ..., (4.M-9) -th elements 10 AND-OR of the first group are connected to the device logical zero bus, the twentieth input (4.M-8) -th element 10 AND-OR of the first group is the twenty-third information in the house of the two-channel switch, the twentieth input of the d-ro element 10 I-IL of the second group is the d-th bit of the twenty-second information input of the two-channel switch, the twentieth inputs of the (4.M-15) -th, (4.M-14) th (4-M-13) -th and (4.M-12) -th elements 10 AND-OR of the second group are the first, second, third and fourth binary bits of the first information input of the two-channel switch, the twentieth inputs ( 4.M-11) -th, (4.M--10) -th, (4.) -Th and (4.M-8) -th elements 10 AND-OR are respectively first., Second, third. and fourth binary the bits of the second information input of the two-channel switch, the input of the k-ro element of the NOT two-channel switch is connected to the second input (kl) -ro of the element AND of the two-channel switch and is the kM control input of the two-channel switch, the input of the first element of the NOT two-channel switch is the first control the input of the two-channel switch, the output of the g-th element 10 AND-OR of the first group is the r-m binary bit - DO.M of the first output of the two-channel switch, the output of the g-th element 10 AND-OR of the second group is the r-m d oichnym discharge dvuhka second output; tional switch. I I LW W.w-2 11 - .. ,, I. I . V . “Id to i (as “A on to (U .Editor E. Smoke Compiled by S. Silaev Tekred M. Khodanych i Order 2986/51 Circulation 671, Subsidiary VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5  - -..-.-- - - - "-" .-. - - “ish. Production and printing company, Uzhgorod, st. Project, 4 Proofreader G. Reshetnik