SU1226659A1 - Device for counting number of pulses in train - Google Patents

Abstract

The invention can be used in automation, telemechanics, measurement and computing. The purpose of the invention is the expansion of functionality and noise immunity. The device contains counters 1, 2 ,. 20, 21 and 25, controlled frequency divider 3, control inputs 4, keys 5 and 9, clock bus 6, triggers 7, 8 and 26, elements 10, 22 and 29 OR, gate generator 12 with outputs 11, 14, 15 and 18, input bus 13, elements 16, 17, 19 and 27 I, bus 23 of the last pulse mark, reset bus 24, tire 28 of the first pulse mark, bus 30 of the single pulse mark and output buses 31 and 32. Introduction to the generator device 12 gates, counters 20, 21 and 25, trigger 7, elements 16, 17, 19 and 27 AND, elements 22 and 29 OR and the formation of new connections between the T1I element provides the possibility of counting the missing x pulses. 3 ill. (L t3 2 // / 5 J8 17 27 about 25 to to Od Od SL CO gZI-J- QK-1 Id Figure 1

Description

The invention relates to a pulse technique and can be used in automation, telemechanics, measurement and computing technology.

The purpose of the invention is to enhance the functionality and noise immunity by counting the missed pulses in a series while improving noise immunity.

Figure 1 shows the structural electrical circuit of the device; figure 2 - timing charts of the device; FIG. 3 shows timing diagrams of the gate generator operation.

The device contains the first 1 and second 2 counters, a controlled frequency divider 3, the control inputs 4 of which are connected to the outputs of the corresponding bits of the second counter 2, and the input with the first code of the first switch 5 with the memorization of the control signal whose switching input is connected. with the clock bus 6, and the control input with the inverse output of the first trigger Vj, the installation input 1 of which is connected to the installation input 1 of the second trigger 8 and the first output of the second key 9 with the control signal memorized not with the direct output of the second trigger 8, the second output with the first input of the first element OR 10, and the switching input with the first output 11 of the generator 12 gates, whose input is connected to the input bus 13, the first output P with the input of the first counter 1 second 14 and the third 15 outputs - with the first inputs, the first 16 and second 17 And elements, respectively, the fourth output 18 - with the first input of the third element And 19 and the installation input in About the third counter 20, the input of which is connected to the output of the third element And 19 and input the fourth counter 21, and the output - with the first I ode of the second element OR 22 and bus 23 marks the last pulse. The second input of the second element OR 22 is connected to the reset bus 24, and the output to the installation inputs of the first 1, second 2, fourth 2 and fifth 25 counters, controllable frequency divider 3 and installation inputs to the second 8 and third 26 triggers. The output of the controlled frequency divider 3 is connected to the second inputs of the first 16, second 17 and third 19 And elements and the input of the fifth counter 25,

five

0

five

0

five

the output of which is connected to the installation input to 1 of the third trigger 26 and the first input of the fourth element I 27, the second input of which is connected to the inverse output of the third trigger 26, and the output to the bus 28 of the first pulse, the second output of the first key 5 with the memory of the control signal is connected with the first input of the third element OR 29, the second input of which is connected to the output of the first element AND 16, and the output to the input of the direct count of the second counter 2, the input of the countdown of which is connected to the output of the second element And 17, and the output to the bus 30 of the label one nocturnal pulse. The outputs of the first 1 and fourth 2 meters are connected respectively to the first 31 and second 32 output buses.

The device works as follows.

In the initial state, the triggers 7, 8 and. 26, the counters 1, 25, and 2 and the controlled frequency divider 3 are set to O by a pulse arriving on the reset bus 24. For the same impulse, an additional sum code (t + 1) is set in the counter 21.

Impulses arriving at the input bus (figure 2 a), start the generator 12 strobes, which forms the outputs P, 14,15 and 18 strobe pulses, the diagrams of which are shown in fig.Zb, c, d. The period of the input pulses in a series can vary from

series to series within (T

The number of pulses in the M series can also vary from series to series, and individual pulses or groups of pulses can accidentally disappear (t is the number of consecutive missed pulses). The intervals between the series of pulses T "are chosen based on the inequality

T (t +1) t

Max

(I)

50

At the output of the generator, strobe pulses are formed (. FIG. 2 d) of duration

(2)

.T ,,,,

where 6m is a given period instability.

55 The pulses at the output I1 of the generator 12 (fig.Zb) have a duration t ,, longer than the period of clock pulses tyy, and are delayed relative to

31

input pulses at time equal to RT, 1 t, 2

The first pulse from the output 1I of the generator 12 is passed with the key 9 to the single inputs of the flip-flops 8 and 7 sets them to 1. The key 9 passes the first pulse to the first output completely and prohibits its passage to the second output. The clock pulses from the bus 6 are transmitted by the key 5 to the input of the direct counting (reversing) counter 2 (Fig. 2.3). When the second pulse of the series arrives at the input bus, a second pulse is generated at the generator output, which is passed by the key 9 to the installation input to the O flip-flop 7, and the pulses from the clock bus 6 begin to receive the second input of the key 5, i.e. to the input of the controlled frequency divider 3. The division factor K is determined by the code accumulated by that time in counter 2 and supplied 1 1 1M to the corresponding control inputs of the divider. 3. Thus, after the time T Kt after the arrival of the second pulse from the output 11 of the generator 12, the overflow signal appears at the output of the divider 3. If the next pulse in the input series is not passed, the overflow pulse enters the forward or reverse counting counter 2 and makes the necessary correction of the counter code 2 and to the input of the counter 25. If the next pulse is missed, then the overflow pulse from the output of the divider goes through the open element 19 and to the inputs of the counters 21 (FIG. 2 d) and 20, and also counter input 25. In either of two Luciano counter 25, frame of reference aB m pulses, generates a pulse supplied to the bus 28. This pulse zader-. regarding the first impulse of the series and the time is equal to T (t + 1) (figure 2 e) and serves as a mark of the first impulse of the series. The remaining overflow pulses of the counter 25 are blocked by the trigger 26 and the AND 2 7 element.

The missed pulses are counted by the counters 20 and 21. The counter 20 is zeroed by the arrival of each iid pulse of the series, and in the series call, counting (t +) the pulse, overflows, and the pulse of its overflow postzg falls on the bus 23 (FIG. ) and serves as a mark of the end of a series of pulses, relative to the last pulse of which

ten

15

266594.

he is arrested on T (m + l). In addition, the overflow pulse of the counter 20 through the element 22 enters the inputs of the installation of the triggers 8,7 and 26, the counters 1, 2 and 2 and 25 and the divider 3 and returns the device to its initial state, thus preparing for the processing of the next series of pulses . In counters 1 and 21, by this time, the codes for the number of pulses in a series (excluding the missed ones) and the number of missed pulses, respectively, accumulate.

If there is a single pulse in the series, then the counter 2 overflows and impulses the pulse to the bus 30 of the label of a single pulse and to the reset and set-up inputs of the elements.

The measurement of period T over the first interval was made with a methodological error & t + t due to quantization. The accumulation of this error can lead to the output of the overflow pulses of the divider 3 from the strobe limits. In order to exclude the possibility of an exit, And 16. and 17 elements, an OR 29 element, are introduced to correct the period code T in counter 2. When a pulse hits the left half of the gate (FIG. 3 in), 1. is added to the code - (K + 1 ). When a pulse hits the right half of the strobe (Fig. 3 d), 1 is subtracted from the code (K-1). The pause between the half-gates is selected from the condition t ty to eliminate the possibility of an overflow pulse in both half-gates. The error is not corrected with a group pass due to the absence of semi-cuts, therefore the duration of iT-t,

20

25

thirty

40

45

half gates

i

break condition

T - tn

must meet

m-jitj

(3)

The strobe durations calculated by formulas 2 and 3 may differ, therefore it is necessary to choose a large

of them.

The proposed device makes it possible to count the number of missed pulses in a series, pre-restoring them. If there are gaps of pulses in a series, the device does not generate false output pulses. The technical advantages of the proposed device, as compared to the well-known ones, are enhanced functionality, namely: the possibility of determining the number of missed pulses in a series, as well as increased noise immunity when the input pulses are skipped.

Claims (1)

Invention Formula A device for counting the number of pulses in a series, containing the first and second counters, controlled by a frequency divider, the control inputs of which are connected to the outputs of the corresponding bits of the second counter, and the input to the first output of the first key with the control signal memorized bus, and the control input - with the scrolling 4 output of the first trigger, the installation input in 1 of which is connected to the installation input in - the second trigger and the first output of the second key with the memory of the control signal, input y the control of which is connected to the direct output of the second trigger, and the second output to the first input of the first element OR whose second input is connected to the installation input of the second trigger O, and the output to the installation input of the first trigger, the output of the first counter is connected to the first output bus, characterized in that, in order to expand its functionality and noise immunity by counting the number of missed pulses in a series, the gate generator, the third, fourth and fifth counters, the third trigger, the first, the second th, third and fourth elements are And, the second and third elements are OR, and the gate generator input is connected to the input the device bus, the input of the first counter and the switching input of the second key with the storage of the control signal are connected to the first output of the gate generator, the second and third outputs of which are connected to the first inputs of the first and second elements, respectively, and the fourth output to the first input of the third element, and the installation of the third counter in O, whose input is connected to the output of the third element I and the input of the fourth counter, and the output to the bus of the last pulse mark and with the first input of the second element OR, the second input of which is connected to the label bus of a single HMnyjTbca and the output of the second counter, the third input - to the reset bus, and the output - to the inputs installing the first, second, fourth, and fifth counters, the controlled frequency divider, and the installation inputs to the second and third triggers, the output of the controlled frequency divider being connected to the second inputs of the first, second, and third elements And the fifth counter, the output of which is connected to the installation input to 1 of the third trigger and the first input of the fourth element is And, the second input of which is connected to the inverse output of the third trigger, and the output - with the label bus of the first pulse, and the second output of the first the key with the storage of the control signal is connected to the first input of the third element OR, the second input of which is connected to the output of the first element AND, and the output to the input of the direct account of the second counter, the counting input of which is connected to the output of the second element AND, the fourth output The meter is connected to the second output bus. {AND I I I Editor A. Sabo Compiled by A. Sazonov Tehred V.Kadar Proofreader A.Ferents 2147/59 Circulation 816 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d. A / 5 Production and printing company, Uzhgorod, st. Project, 4 in. FIG. 2 Fi & .З