SU1226450A1 - Generator of random numbers with gaussian distribution - Google Patents

Abstract

The invention relates to the field of computer technology and can be used to determine the impulse transient characteristics of various dynamic systems in identification tasks. The purpose of the invention is to increase the speed for. by using the fast ordinate formation algorithm of a normally distributed random process. The generator contains a sensor of uniformly distributed random variables, an adder, a group of multiplexers, a memory unit, a group of elements EXCLUSIVE OR, the first and second memory registers, a synchronization unit, a control unit of a random process memory unit. At the first stage, the ordinates of a uniformly distributed process are recorded in the memory block. After filling the memory block, the device implements n steps of the fast conversion procedure. Under the action of clock pulses entering the memory control node, memory block, first and second memory registers, adder, group of EXCLUSIVE OR elements, the ordinates are formed normally distributed random process. 4 il. c (L GcHE N3 O 4ii. SL

Description

one

The invention relates to the field of computer technology and can be used to determine the impulse transient characteristics of various dynamic systems.

The purpose of the invention is to increase the speed of the device.

Figure 1 shows the functional diagram of a generator of normally distributed random numbers; figure 2 is a functional diagram of the synchronization unit; in fig. 3 is a functional diagram of the memory management unit; 4 shows timing charts of the synchronization unit.

The generator contains a sensor 1 of uniformly distributed random variables, a group of multiplexers 2, a memory block 3, registers 4 and 5 memory, a group of EXCLUSIVE OR elements 6, an adder 7, a synchronization block 8, a node 9 of the control of the memory block.

The synchronization unit 8 contains two one-stroke T-flip-flops 10 and 11, the EXCLUSIVE OR 12 element, the IL-NOT 13 element, the HE element 14, AND 15-15 elements, the HE elements 19 and 20.

The memory unit control node 9 contains an OR element 21, a circular shift register 22, a group of EXCLUSIVE OR 23 elements, a multiplier 24, adders 25 and 26, binary counters 27-29, trigger 30, elements AND 31-35, multiplexer 36, an EXCLUSIVE element OR 37, the element is NOT 38, the element is OR-NOT 39.

The memory management node works as follows.

In the initial state, in all binary counters of node 9 a zero code is written, in the higher bit X of the ring shift register 22 is written 1, the trigger 30 is set to O. With the code 00 on the control inputs of multiplexer 36, the outputs of the binary counter 27 and the EXCLUSIVE OR 37 element are connected to the address input of the memory unit. Zero at the first input of the element OR 21 permits the passage of pulses from the second output of the synchronization unit at the clock input of the binary counter 27. At the outputs of the binary counter 27 and the EXCLUSIVE OR 37 element, the addresses of the zero permutation step of the computational procedure are written. All implementations are divided into blocks of four samples, among which permutations must be made. If the reference number and the address at which it will be written to the memory block are represented in binary code, the permutations will be reduced to recoding the two least significant bits according to the following scheme;

Reference number ХХОО 001 ХХ10 ХХ11

Address operand XXOO 0010 XXI 1 ХХ01

five

0

five

where XX is the high bit code.

After filling the information of the memory block at the output of the high bit of the binary counter 27, a trigger sets 30 to 1. Where element OR 21 prohibits the passage of pulses to the clock input of the binary counter 27, and element 33 allows the clock to pass from the first output of the synchronization unit The clock input of the counter 28, AND 31 permits the passage of pulses from the third output of the synchronization unit to the control; i, the input of the multisexor 36. 1 at the control input of the higher bit of the multiplexer 36 permits Connection to the input of the memory block of adders 25 and 26. Counter 28 generates the current value of the variable j according to the recurrent relations

b-X {J +, 2). to +1

X (; ,,, Л,.,. ..1 PK,

0

five

- X {l +; ((l +, 2

- X (J

where X - n - k 1

J 1

n - to t 1.

t 2

h-k

- X (j + i 2 K + 1

 K.

0

and to 0 ,.

address operand, p fogjN; the number of binary bits, the step number of the computational procedure,

the number of the split interval is the length1 of the implementation on the Kth step, the reference number on the split interval i,

ir; i oh j

The upper limit of the change j is given by the code at the output of the shift register 22. The counter 29 forms the current 55 ALTERNATIVE variable i, which alternates with the code coming from the output of the shift register 22. The received code goes to the first input.

3

adder 25, the second input of which receives the variable j code, while the output of the adder 25 forms the address of the first operand, which goes to the first inputs of the multiplexer 36 and the adder 26, the second inputs of which receives code 2 At the output of the adder 26, the address of the second operand is formed. The addresses of the operands arrive at the output of the multiplexer 36 in accordance with the timing diagrams (figure 4). At a low signal level, at the second input of the And 31 element, the code of the first operand arrives at the address input of the memory block, and at a high level, the code of the second after generating the last address of any step (except zero) of the computational procedure, the output of the And 34 element will generate a pulse the counter 29 is set to O will shift the contents of the ring register 22 to the right by one bit. After the last n-th step of the computational procedure is completed, if 1 is present in bit X of the shift register 22, it will be set to O three ger 30. Thus, the control unit memory node is again ready for operation.

The generator works as follows.

At the zero step, the clock pulses from the second output of the synchronization block are written to the ordinates of the uniformly distributed process in the memory block 3. After the memory block is filled with a high level at the control input of the group of multiplexers 2, the output of the adder 7 is connected to the information input of the memory block and the device implements the K steps of the fast conversion procedure according to the time diagrams (Fig. 4). The node 9 generates the address of the first ordinate, which is written to the register 4 by the first clock pulse. By the second clock pulse, the second ordinate is written to the register 5, the code of which groups of elements EXCLUSIVE P1LI 6 is inverted and added to the transfer bit from the lower digit of the adder 7 1, thus, at the output of the adder 7, the difference of the ordinates is formed, which is recorded at the third clock pulse by the memory block at the address of the second ordinate. Further, when sig26450 is low

At the third output of the synchronization unit, the sum of the ordinates is formed at the output of the adder 7 and recorded at the address of the first ordinate. The formation of the following ordinates will occur in a similar way, i.e. for every four cycles, two ordinates of the corresponding procedure step will be formed. At the last step of the computational procedure, the ordinates of a normally distributed random process will be formed at the output of adder 7 sequentially after two cycles.

15

Claims (1)

Invention Formula A generator of normally distributed random numbers, containing a 2Q sensor of uniformly distributed random variables and an adder, characterized in that, in order to improve speed, a group of multiplexers, a memory block 25, a first and second memory registers, a group of EXCLUSIVE OR elements are entered into it. , synchronization unit and memory control unit, containing- PNI element, ring shift register, multiplier, first and second adders, first, second and third counters, trigger, first, second, third, fourth and fifth elements, m Liplexer, EXCLUSIVE OR element, NOT element, element group 35- CLASSIFOR OR, WI-HELL element, and the first output of the synchronization unit is connected to the first input of the first AND element of the control unit of the memory unit, the output of which is connected to the clock input of the first counter and the first input of the second element And, the second input of which is connected to the output of the element of NRN-NOT, the inputs of which are connected to the outputs of the elements. EXCLUSIVE OR groups of the control unit of the memory unit, the first inputs of which are connected to the first group of inputs of the first adder of the control unit of the memory unit and to the output of the first counter, the installation input of which is connected to the output of the second element And the clock input of the second counter, output which is connected to the first input of the multiplier, the output 55 of which is connected to the second input of the first adder of the control unit of the memory block whose output is connected to the first information input thirty 40 five the multiplexer of the control unit of the memory unit and the first bit input of the second adder, the second bit input of which is connected to the second inputs of the EXCLUSIVE OR group of the control unit of the memory unit, the second bit input of the multiplexer and the bit output of the ring shift register with the shift one bit to the right, the output of the zero bit of the ring shift register is connected to the first input of the third element I, the second input of which is connected to the clock input of the ring shift register, the setting inputs of the second and tchiko and connected to the output of the fourth element And, the first inputs of which are connected to the output of the second adder and the second information input of the multiplexer, the third information input of which is connected to the outputs of the higher bits of the third counter, the first bit output of which is connected to the first input of the element that EXCLUSIVE OR or to the zero bit of the third information input of the multiplexer, the first bit of the third information input of the typelexer circuit is connected to the gold output of the EXCLUSIVE OR, the second input It is connected to the zero discharge output of the third counter, which ht.cot input is connected to the output of the OR element, the first input of which is connected to the second output of the synchronization unit and the second input of the fourth element AND, the third input of which is connected to the output element is NOT, the output of the third element is AND is connected to the trigger input of the trigger, the setup input of which is connected to the output of the last digit one third 6 its counter, the trigger output is connected to the second input of the OR element and to the first bit of the control input of the multiplexer, the second input of the first AND element, the first input of the fifth AND element, the control inputs of the group multiplexers, the second input of the first element AND and connected to the third output of the synchronization unit connected to the second input of the fifth element I, the output of which is connected to the zero position of the control input of the multiplexer, the output of which is connected to the address input of the memory unit, output to which is connected to the information inputs of the first and second memory registers, the output of the first memory register is connected to the first input of the adder, the output of which is the generator output and connected to the first information inputs of the multiplexers of the group, the outputs of which are connected to the information input of the memory block, clock input the second memory register is connected to the fourth output of the synchronization unit, the output, the second memory register is created with the second inputs of the EXCLUSIVE OR elements of the group, the outputs of which are connected to the second y input of the adder, a fifth output synchronization unit connected to the input sensor Poll uniformly distributed random variables, whose output is connected to the second data inputs of the multiplexers group clock input is a clock sync block generator input and the output of the fourth sync block. connected to the clock input of the second memory register. Fig2 HZ. JmAAAAAAfiAAAA.  -n Jt -Mt I r n Jl GT 44T141. J J L 1 14 1-1 Compiled by I. Table mover Editor T. Kugrsheva Tehred V. Kadar ° PP® ° P f f  -. - -. - -------------- - - - Order 2134/48 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, 4/5 Industrial printing enterprise, Uzhgorod, st. Project, 4 (Put. V