SU1225012A1 - Multidigit counter - Google Patents

Abstract

The invention relates to a pulse technique, in particular to pulse counters with non-destructive information. It can be used in automation devices where high reliability is required. The purpose of the image. reteni — improving reliability and expanding functionality — is achieved by reverse counting and the presence of a galvanically developed output in binary code. The device contains a power source, a pulse shaper 1, a pulse separation unit 2 into even and odd discharge cells ... connected in series, and a reversing unit 4, polarized relays 5-8, and contacts 9-60. The operation of the device is explained in the time diagrams in the description of the invention. 1 hp ff, 2 ill. cl

Description

The invention relates to a pulse technique, in particular to pulse counters with non-destructive information, and can be used in automation devices where high reliability is required.

The aim of the invention is to increase the reliability of the counter and to expand the functionality due to the reversible counting and the presence of a galvanically developed output in binary code.

FIG. 1 shows the proposed device; in fig. 2 - time diagram.

The counter includes a power supply E, a pulse shaper 1, a pulse separation unit 2 into even and odd bit cells. .. connected in series and block 4 revers, polarized relays 5-8, relay contacts 9-66.

The device works as follows.

All elements are shown in storage mode (code Q, Qj. ... O) when ce 1 is de-energized. In this mode, counting pulses do not affect the state of the device. They also do not affect the RF switch position of unit 4 when, in the intervals between pulses, the power supply circuit of the return winding of unit 2 is assembled, and in pulses the voltage is applied to both successive power circuits. break contacts of cells .... From this state, the counting is possible only on addition. The switch of the block 4 to the position of the SL (necessarily in the pause between the pulses) at this point is assembled the power supply circuit of the winding of the actuation of the block 2, which switches to the operating position. When the actuator 1 is first triggered, the current in the circuit is: contacts 9 and 10 - relay 6 actuation winding - opening contacts of cells 3-2 ..., the cell is transferred to the working position. In this case, the output of Q, appears level log.1 (log. D 45, 43, 33, 31, 25, 24). In the pause after the first pulse, block 2 returns to its initial state. From the second impulse, the cell is triggered (circuit 9, AND, 15 and 16 are energized, relay 7 actuation coil, opening contacts ...). In this case, the output of Pr appears level log.G (log.

It reads 2 1 45, 43, 35, 34), and the output of Q is the log.O (log. About 48, 46, 32, 31, 25, 24). In the second pause, the actuation coil of the relay 5 of unit 2 operates, preparing the circuit (12 and 13, return coil of the cell return relay 6, 58, 59, 61, 63) during the third pulse and further according to the Gray code (Fig. 2 a). In this case, the logic levels at the outputs of the cells change in accordance with the N-bit binary code for all co (Fig. 2b). Pulse counter 1 pulses before the appearance of a code. . .0 (, log. 1. At the same time

5, the 3-N cell is in the working position, the remaining cells and block 2 are in the initial position. From this state, the counting is possible only for subtraction, if the switch of block 4 is put in

0 position HF.

The main advantage of this counter is the use of only a relay in it, moreover, one per discharge. Use of polarized

5 relays provide information storage during power interruptions. When increasing the counter size, the power of the power source is not required to increase. Single type bit cells

0 improves the performance of the device. Account reversal and the presence of galvanically developed output in binary code for all combinations expands the functionality of the counter. The peculiarity of the counter is its self-stopping in the code ... 1 when adding, in the code Q p2 .... About when subtracting.

five

Claims (2)

1. A multi-bit counter containing bit cells assembled into a serial counting circuit by connecting the corresponding outputs and inputs of neighboring cells, each of the cells is made on a polarized relay with switching contacts and separate actuation and return windings, first, second, third and fourth the cell inputs are respectively the switching contacts of the first, second, third groups and the start of the actuation winding, and the first, second, third and fourth outputs of the cell are respectively p zmykayuschy first contact group coupled to the secondary contact zamykayuE1Im Group of switches, opening contact of the second group, connected to the closing contact of the first group, opening and closing contacts of the third group, characterized in that, in order to increase reliability and expand functionality, the fifth and sixth inputs of the discharge cell are respectively the beginning the return windings and the switching terminal of the former are connected the fourth cycle, the counter is complemented by a block of section & shadow of the counting pulses, the ends of the windings of the polarized relay of which are connected to the first and second inputs of the low-order cell, the closing contacts to the third and fifth inputs of the low-order cell, and disconnecting contacts to the fourth and the sixth inputs of the low-order cell, a pulse shaper, the outputs of which are connected to the corresponding inputs of the separation unit of the counting pulses, and a power bus connected to the input, and a reverse unit, the inputs of which are connected to the first mu and second outputs of MSB cell, and an output coupled to common power bus, the winding ends of said actuation and return are connected to respectively pervoyZO break contacts of that group, and the NC contact and the second group, and the fifth and sixth of the sixth group, connected to the 1st the moves of the cell are the corresponding contact of the fifth group, and but closing and opening contacts fourth group, first 1m and third, The second and fourth inputs of the block are separate busbars, and the seventh and eighth counts of counting pulses are my cell inputs that are paraphase, respectively, the beginning of the windings and the logical outputs of the corresponding processing and return, switching bits. the seventh and eighth outputs of the high-order cell are connected to the paraphase the contacts of the first and second groups, the pulse shaper are made on two mechanically connected switching contact groups, the first and second, third and fourth outputs of the shaper are respectively the opening and closing contacts of the first group, the opening and closing contacts of the second group, and the switching contacts of both groups, the reverse unit is made on a three-position switch with self-return to the neutral position, the first and second inputs of the reverse unit are the closing contacts switching to n clock cycle is output. I 2. The device according to claim 1, characterized in that, in order to expand the functionality, its cell discharge is supplemented with the seventh and eighth inputs, which are considered to be the switching contacts of the fifth and sixth groups, respectively, and the seventh and eighth outputs, which are respectively, the opening contact of the fifth group, connected to the closing contact of the sixth and eighth outputs of the high-order cell, are connected to the paraphase ones  LiShPLShShLSh11Sh1Sh   JTTlJTTUbriJlJinJlJ 5-4 Q1 -JIJIJIJIJIJIJIJIJT g 3 J one J J one 4 5 J (pue.Z