SU1221611A1 - Phase metering device - Google Patents

Abstract

The invention relates to a technique for measuring the phase of radio signals. The device contains a discriminator 1, reversible counters 2 and 7, elements OR 3, 4, 5, 6 and 20, a disk phase shifter 8, a reference generator 9, a divider 10, an indication unit 11, a decoder 12, an inverter 13, keys. 14 and 15, an input 16 of setting pulses, a trigger 17, elements AND 18 and 19. Operation of the device according to different algorithms with large and small phase mismatch between the reference generator 9 and the external signal reduces the time taken to measure the signal phase. In the description given the calculation of the time of the working phase. 1 il. (L Yu O)

Description

The invention relates to a technique for measuring the phase of radio signals and can be used in the equipment of receiving stations of radionavigation systems.

The purpose of the invention is to reduce the phase measurement time of a signal.

The purpose of the invention is achieved due to the operation of the device according to different algorithms with large and small phase mismatches between the reference generator and the external signal

The drawing shows a block diagram of the phase meter device

The device contains a phase discriminator 1, the outputs of which are connected to the summing and subtractive inputs of the reversing counter 2, the outputs of which are connected to the first inputs of the SHSh 3 and 4 elements and the OR 5 and 6 elements. The outputs of the latter are connected to the subtracting and summing inputs of the reverse counter 7, and the control inputs of the discrete phase shifter 8 are connected to the outputs of elements OR 3 and 4, the signal input of the phase shifter 8 is connected to the output of the reference oscillator 9, and its output is connected to a frequency divider 10. The latter is further connected to the input signal of the discriminator 1 and the unit 11 pulse setting. The output of the key 15 is connected to the installation input of the reversible counter 7, and its control input is connected to the output of the inverter 13. The output of the key 14 is connected to the input of a single installation of the trigger 17, the output of which is connected to the first inputs of the And 18 and 19 elements. The second inputs of the And 18 elements and 19 are connected to the outputs of the reference generator 9, and their third inputs are connected to the second and third outputs of the decoder 12. The inputs of the OR element 20 are connected to the outputs of the reversible counter 7, and its output is connected to the input zero. The first trigger setup 17. The outputs of the elements 18 and 19 are connected to the second inputs of the elements OR 4 and 3 and to the second inputs of the elements OR 5 and 6, respectively.

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The device works as follows.

At the initial measurement time, the reversible counter 7 is in the wound state, and the trigger 17 is in the zero state. The first input of the phase discriminator 1, which is the input of the phase metering device, receives a received signal (in a mixture

10 with noise) and is compared in phase with the reference signal supplied to the second input of the discriminator 1 from the frequency divider 10. According to the results of the comparison on the first and second outputs

15 discriminator 1, a series of pulses are formed, arriving at the summing and subtracting inputs of the reversible counter 2 o With the outputs of the counter 2 pulses through the elements OR 3 and 4

20 are fed to the control inputs of the discrete phase shifter 8 and through the elements OR 5 and 6 to the inputs of the reversible counter 7. The input of the discrete phase shifter 8 is received

25 pulses from the reference oscillator 9. The arrival of a pulse at the first control input of the phase shifter 8 leads to a shift of the pulses at its output and a shift of the reference signal by

The 30 output of the frequency divider 10 to the right to the discrete equal to the frequency period of the reference oscillator 9. A pulse arriving at another control input of the phase shifter 8 shifts the reference signal to the same discrete left.

Reverse Counter Capacity 7

is chosen so that over a time interval equal to the period between the pulses of the setup from input 16 (Tyj,), it does not overflow with any phase mismatch between the received and reference signals.

With significant phase mismatches in the interval (T), the number of pulses coming from one of the outputs of counter 2 through the corresponding element OR 5 and 6 to the input of counter 7 is large. Then the absolute value of the number recorded in the counter 7 at the time (T) from the beginning of the measurement (at the moment of arrival of the pulse from the input 16) exceeds the threshold value. In this case, from the first output of the decoder 12 to the control input of the key 14 and the input of the inverter 13, a high potential flows, and from the output of the inverter 13 to the control input of the key 15 - low. Key 15;

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opens and does not transmit a setting pulse to zeroing the reversible counter 7. From the output of the closed key 14, the installation pulse enters the input of the single installation of the trigger 17. The high potential from the trigger 17 goes to the first inputs of the And elements 18 and 19. The second inputs of the And elements receive pulses from the reference generator 9, and to the third input of one of them (depending on the sign of the number) - high potential from the corresponding output of the decoder 12. With a positive sign of the number, the high potential from the second output goes to the third input ementa and 8. The pulses output from the reference oscillator 9 pass through the AND gates 18 and OR 4, 5 and come out. the first control input of the phase shifter 8 and the subtracting input of the reversible counter 7. Each of these pulses, coming through the element OR 5, leads to a decrease in the number t recorded in the counter 7, When the counter 7 is zeroed, an impulse is formed at its output 20 arrives at the zero input of trigger 17, whence comes the low potential at the input of the element And 18 and prohibits the passage of pulses to its output. Thus, at the output of the element And 18, a burst of pulses is formed, which causes the reference signal to shift through the element OR 4 by means of the phase shifter 8. The number of pulses in the packet is equal to the number recorded in counter 7 at the moment of the installation pulse. If negative number is fixed in counter 7, From the third output of the decoder 12, a high potential arrives at the third input of the element AND 19. The pulses from the reference generator 9 pass through the elements AND 19 and OR 3, 4 and arrive at the second control input of the phase shifter 8 and add up s input of down counter 7, which leads to a decrease in absolute value in the counter 7. When the zeroing pulse counter 7 with its output passes through OR gate 20 and sets flip-flop 17 to the zero state. In this case, the passage of pulses through the element AND 19 stops. The number of pulses in a packet formed at the output of the element And 19 is equal to the absolute

the value of the number fixed in the counter 7. When a batch of pulses arrives from the output of the element AND 19 through the element OR 3 in the correction interval (T), the reference signal receives the same shift as in the previous interval between the pulses of the setting (Tu). The directions of the shifts also coincide.

The magnitude of the interval (T) is chosen so that the shift (magnitude of testing) uf of the reference signal in the interval (T) is approximately equal to half the initial error

(bj) At the same time, the subsequent correction by a burst of pulses from the output of elements AND 19 (or 18) provides, with a certain error, a combination of signals. If there is no noise,

then the magnitude of the phase mismatch between the signals in the interval (T,) varies according to the experimental value. The value on the interval (T) is determined by the formula

. (1 -e if),

where t is the time constant of the phase meter device.

Given UVfo g, we find T.

 t, fpln2. In the presence of noise and Tu.,. , and the value of phase mining is equal to

Dc ogp

- + H,

SlL

where rf srd is random, equal to noise fluctuations

phase reference signal.

The magnitude of the phase mismatch between the signals after correction dCH p is equal to -. Mathematical expectation D -f is equal to

zero, the rms value is twice the noise fluctuations of the phase of the reference signal (cf „). A small phase mismatch, which may occur after a shift of the reference signal, is quickly resolved. At the end of the test, the phase of the reference signal (coinciding with the phase of the input signal) is recorded in the display unit 11. Time to change

The phases of the received signal can be considered equal to 2Tu, 21п1. With minor phase mismatch x dch 446 gm on the interval

() the number of pulses coming from the outputs of counter 2 is small and the number in counter 7 at the time of the installation pulse does not exceed the threshold value. In this case, low potential flows from the first output of the decoder 12 to the control input of the switch 14 and the input of the inverter 13, and from the output of the inverter 13 to the control input of the switch 15 - high. The key 15 is closed, and the setup pulse from input 16 passes through it to zeroing the counter 7. The setup pulse does not pass through the open key 1A, and the trigger 17 remains in the zero state. The correction of the reference signal through the AND element is not carried out at the same time, and the development of the initial mismatch occurs according to a law close to the exponential Time of the (measuring) phase in this case can be considered to be equal to 2Т 21п2.

And at any initial mismatch, the phase measurement time T% ft: 21n2i p.

Claims (1)

Invention Formula Phasometric device containing a series-connected reference oscillator, a discrete phase-shifter and frequency divider, a phase discriminator and a first reversible counter, as well as a second reversible counter, a decoder, first and second keys and a display unit, with the display outputs of the second reversible counter connected to the inputs decoder signal inputs Editor T. Mitejko Order 1609/52 Compiled by V. Shubin Tehred n. Bonkalo Proofreader L. Patay . Circulation 728 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Branch PPP Patent, Uzhgorod, st. Project, 4 the keys are connected to the input of the pulses, the control input of the first key is connected to the first output of the de-5 encoder, and the input of the display unit is connected to the output of the frequency divider and the input of the phase discriminator, in order to reduce the measurement time } 0 of the phase of the signal, five elements of SH, two elements AND, an inverter and a trigger are entered into it, the first inputs of one of the two elements OR are connected to the outputs of the first reversing 15 counters, their second inputs are with the outputs of the first and second elements I, respectively, and the outputs are connected to the control inputs of the discrete phase shifter, the first inputs of the others 20 two elements OR are connected to the outputs of the first reversible counter, their second inputs to the outputs of the second and first elements AND, respectively, and the outputs to the inputs 25 of the second reversible counter, the first inputs of the And elements are connected to the trigger output, their second inputs are connected to the output of the reference generator, and the third to the second and third to the 30 outputs of the decoder, the outputs second reversible counter soy-. dineny with the inputs of the fifth element OR, the output of which is connected to the input of the zero installation of the trigger, - single trigger input connected to the output of the first key, the control input of the second key through the inverter is connected to the first output of the decoder, and its output to 0 input installation of the second reversible counter.