SU1220123A1 - Multichannel switching device - Google Patents

Abstract

The device relates to electronic switching technology and can be used for the initial processing of analog signals in multichannel data acquisition and distribution systems, in particular, for controlling matrix solid-state photodetectors. The purpose of the invention is the expansion of functional capabilities by polling channels with a simultaneous shutdown, as well as shutting down and shunting the required number of unprovable channels, is achieved by introducing an additional shift register and implementing a channel selector unit in the form of a device that allows the combined switch keys of the switch. The operation of the switch is explained in the functional diagrams and table given in the description of the invention, 1 3.p. f-ly, 1 tab. 2 Ш1, i (Л h ю k ND СО

Description

i

The invention relates to electronic switching technology and can be used for the preprocessing of analog signals in multi-channel data acquisition and distribution systems, in particular, for controlling matrix solid-state photodetectors.

The purpose of the invention is to expand the functionality of the switch by polling the specified channels while simultaneously disconnecting and disconnecting and shunting the required number of unsupplemented channels by introducing an additional shift register and implementing the channel selector as a device that allows for combined control. switch channel keys.

Figure 1 shows the functional diagram of the switch; 2 is a schematic diagram of a single channel code converter.

The device contains the first 1 and second 2 shift registers with parallel reading of all h bits in the forward and inverse transducers, h transducers 3 codes, n groups of logic elements 4, channel selection device 5, bus 6 prohibition, first 7 and second 8 analog keys, input buses 9 channels, the first 10 and second 11 output buses of the switch.

Information inputs of the first and second registers are connected to information buses 12 13, and the inputs for setting the first and second registers to zero are connected to the first 14 and second 15 installation buses to zero,

The clock inputs of both registers are connected together and connected to the clock bus 16, the polling permission inputs of both registers are connected to the poll enable bus 17, the unit setup input of the second register is connected to the unit installation Epine 18. Bus 6 ban connected to the inputs of all elements And m groups of logic elements 4. The source of that 1 1-channel transistor code converter is connected to the bus 19 of zero potential. Information outputs of the first and second registers are connected to the output information.

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20 and 21 respectively.

In each i-th channel (i 1, 2,.,., And) the direct and inverse outputs of the same name of the first register are connected to the first 22 and second 23 inputs of the converter of the 3 code, and the direct and inverse outputs of the same name of the second Register - with the third 24 and fourth 25 inputs, respectively. A direct output of the same name of the second register, connected to the third input 24 of the code converter, is connected to the first input of the first element AND of a group of logic elements 4. The second input of the first element And is connected to the inverse inputs of the second and third elements AND of this group and with common for all channels bus 6 ban. The first 26 and second 27 outputs of the code converter are connected to the direct inputs of the second and third elements AND of the group of logic elements 4, respectively. The outputs of the first and second elements AND a group of logic elements 4 are connected through the OR element to the control input of the first analog switch 7. The output of the third element AND is connected to the control input of the second analog switch 8.

The code converter 3 (FIG. 2) contains the first 28, the second 29, the third 30, the fourth 31, the fifth 32 h-channel transistors, the first 33 and the second 34 p-channel transistors, as well as the common bus 19. The drain of the first h- the channel transistor 28 is connected to the first output 26 of the code converter and to the drains of the first P-channel transistor 33 and the second n-channel transistor 29, the source of which is connected to the zero potential bus 19. The gates of the first l-channel 28, first P-channel 33 transistors, as well as the sources of the second p-channel 34 and third P-kangshny 30 transistors are connected to the first input 22 of the code converter. The source of the first h-channel transistor 28 is connected to the drain of the fourth n-channel transistor 31, the source of which is connected to the second input 23 of the code converter. The gate of the fourth h-channel transistor 31 is connected to the source of the first P-channel transistor 33, the gate of the third h-channel transistor 30 and to the third (B input 24 of the code converter. The gates of the second P-channel 34, the second 29 and the fifth 32 h -channel transistors are connected to the fourth input 25 of the code converter. The source of the fifth h-channel transistor 32 is connected to the bus 19 of zero potential, and its drain is connected to the drains of the second p-channel 34 and the third h-channel 30 transistors, as well as the second output 27 code converter.

The device works as follows.

If there is a high-resolution enable voltage on the bus t7 of the polling resolution and a low voltage on the bus 6, the control signals of the i-th switch channel, coming to the information buses 12 and 13, respectively, of the first 1 and second 2 registers, are on the leading edge ( clock signals are synchronously recorded in the i-th cells of these registers.The corresponding signals from the direct and inverse outputs of these cells are fed to inputs 22-25 of the 3 converter of the code, which converts the information in the same cells of registers 1 and 2 into signals y control by analog keys. The control signals of analog keys from the first 26 and second 27 outputs of the converter 3 code through a group of logic elements 4 via TynaiipT to the control 1e inputs of the first 7 and second 8 analog keys, respectively.

On the leading edge of the (i + 1) -ro clock signal, information from the i-th register cells is overwritten into (| +1) cells, and in the i-th cell information is overwritten with (-1)

the cells. Thus, each of the device channels, including the respondent, is controlled by the corresponding signals for a time equal to the period of the clock signal T.

The operation of the code 3 transducer of the 4th channel, as well as the state of the analog switches 7 and 8 of the corresponding channel, depending on the signals,

incoming from the direct and inverse outputs of the same cells of both registers to the inputs 22-25 of the code converter, and from the voltage level on the bar 6 of the ban is illustrated

table (O and 1 - low and high voltage levels).

Is closed

Converter 3 operates in such a way that with four combinations of its input signals coming from the direct and inverse outputs of the same cells in both registers, the outputs 26 and 27 will have three combinations of control signals of the analog switches: simultaneously, the outputs at both outputs 26 and 27 are set to low level; the first output voltage 26 is set to a high voltage; and the second output 27, a low voltage, the first output 26 is set to a low voltage, and the second output 27 is a high voltage. on the level.

As can be seen from the table, the low-level voltage is simultaneously set at both outputs 26 and 27 of the converter 3 if the low level voltage is recorded in the corresponding cell of the second register 2. In this case, the third 24 and fourth 25 inputs of the converter receive low and high levels respectively (Fig. 1) and, regardless of the information recorded in the same cell of the first register 1, the h-channel transistors 29 and 32 are open. Through these transistors, the low level voltage from the common bus 19 is transmitted to both outputs 26 and 27 (Fig. 2).

The high level voltage at one of the outputs 26 and 27 of the converter 3 is set if a high level voltage is recorded in the corresponding cell of the second register 2. At the same time, the third 24 and fourth 25 inputs are supplied to the high and low levels, respectively (FIG. 1), and the transistors 29 and 32 are closed, and the transistors 30, 31 and 34 are opened (FIG. 2). The voltage levels established in this case at the outputs 26 and 27 of the converter are determined by the information recorded in the cell of the same name of the first register 1. If the cell of the same name of the first register 1 contains a low voltage, the inputs 22 and 23 receive the voltages of low and high levels (fig.O, as a result of which opens the P-channel

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the transistor 33, through which from the input 24 to the first output 26 of the converter 3, receives a high level voltage. At the same time, from the input 22, through the open h-channel 30 and P-channel 34 transistors, a low voltage is applied to the second output 27. If the cell of the first register 1 has a high voltage, the high and low voltages are input to the inputs 22 and 23 and the channel transistor 28 opens and the p-channel transistor 33 closes. . As a result, from the input 23 of the code converter 3 through the open h-channel transistors 31 and 28, the first output 26 of the converter 3 receives the low voltage, and from the input 22 through the open i-channel 30 and P-channel 34 transistors to the second output 27 - for example high level. If, at a low voltage level on bar 6, the bar on either of the outputs 26 and 27 of the converter 3 or on both simultaneously sets a low voltage level, then the corresponding n.riie analog keys are closed, and if one of these outputs has a high level matching analog key open. With four combinations of input signals coming from the same cells of both registers, the analog switches 7 and 8 can have the following three general states: at the same time both analog switches 7 and 8 are closed, the first analog switch 7 is open and the second analog switch 8 is closed , the first analog key 7 is closed, and the second analog key 8 is open.

Thus, at a low voltage level on the bus 6 prohibiting the closing of both analog switches 7 and 8 of the I -th channel, it is ensured that the second register is written low to the same level in the cell of the same name and does not depend on the information recorded in the cell of the first register of the same name. The opening of one of the analog keys is provided by writing to the appropriate cell of the second high-voltage register, the first analog key 7 being open when written in the cell of the same name

the first register of the voltage of the low level, and the second analog key 8 - with the voltage of the high level recorded in this cell.

When the voltage is high on the suppression bus 6, regardless of the information recorded in the i-cell of the first register, the following key states 7 and 8 are possible: both analog keys 7 and 8 are closed if the low-level voltage is written in the second register of the same register ; The first analog key 7 is open, and the second analog key 8 is closed if a high level voltage is recorded in the second register of the same name cell.

Disable the second analog key 8 and enable the first analog key 7, i.e. disconnecting the channel on the second output 11 and shunting it on the first output 10 when the voltage is high on the bus

A 6 ban, unlike the same state of these keys with a low voltage on the bus 6 of the ban, occurs when cell information is stored in the cells of both registers 1 and 2 corresponding to the address of the channel polled on the second output 11.

The structured organization of the proposed device ensures its operation in the serial polling channel mode, the parallel polling mode of multiple channels while managing the serial code (serial code-converter mode), the I group polling mode. In the serial polling mode, the device can work:

a) With the disconnection of unprovable channels on the first output 10. This mode is provided by feeding the first constant voltage low register to the information bus 12. Channel polling is performed by high-level signals fed to the information bus 13 of the second register. At the same time, in the sequentially polled channels, the first analog switches 7 (interrogation of channels on the first analog output 10) are open, and in all non-polled channels both analog keys

7 and 8 are closed.

b) With the disconnection of unpredictable channels on the second output 11. This

the mode is provided by supplying the information bus 12 of the first register of high voltage constant voltage from a high level. Channels, as in the previous case, are polled by high-level signals fed to the information bus 13 of the second register. In the sequentially op-ed channels, the second analog keys 8 are open, and in all non-polled channels both analog keys 7 and 8 are closed.

c) With disconnection and shunting of unpredictable channels. The

the mode can be implemented when polling channels both on the first 10 and on the second 11 outputs. The mode is provided by supplying the second high voltage constant-voltage register to the information bus 13. Channels are polled on the first analog output 10 by low level signals, and channels are polled on

5 to the second analog output 11 is carried out by high level signals.

When polling channels on the first exit 10 in the sequentially polled channels, the first

0 tax keys 7, in all non-polled channels - the second analog keys 8, and when polling channels on the second output 11 in the sequentially polled channels the second ones are open

5 analog keys 8, and in all non-polled channels - the first analog keys 7.

d) With simultaneous disconnection, and also with disconnection and shunting of unprossed channels (combined control of analog keys). This mode (similar to the previous one) can be implemented with ohpoce switch channels as

5 on the first 10, and on the second 11 1 outputs.

The mode is provided by applying to the information bus 13 a second high-level control signal register, which, by the duration, overlaps the control signal received by the first number of clock signals on the information bus 12 of the first register. In the case of polling channels on the first output 10, a low-level control signal is sent to the information bus 12 of the first register, and when polling channels on the second

The 1 1 output is a high-level control signal. The frequency of the polled channels on one of the analog outputs 10 and 11 is determined by the number and duration of the corresponding control signals; arriving at the information bus 12 of the first register and coinciding in time with the control signal of a high level on the information bus 13 of the second register The number of channels in the off and shunting state is determined by the total number of clock signals intersected by the control signal of high level arriving at the information bus 13 of the second register before and after the polled channel. The remaining channels are disabled on both outputs.

The front and rear edges of the control signal g entering the second register information input 13, you can adjust the number of channels that are in the shutdown and shunting state and also in the shutdown state on both outputs both before and after the polled channel.

In the sequential pulse mode, when low-level voltage is applied to the interrogation bus 17, information in all bits of both registers, and consequently, the state of all channel keys, is saved as if the clock signals were received on the clock bus 16. and when applying a low voltage to it.

In the parallel polling mode of several channels on one of the outputs 10 and 11, when controlling the serial code and temporarily separating the recording of information and polling the channels, the device works as a serial-to-parallel converter for parallel code. At the same time, the recorded information is represented as corresponding; skinny signals that are fed sequentially to the information bus 12 of the first pe ™ r-ruster while simultaneously feeding the second bus to the information bus 13; low voltage gistra After the information is recorded in the first register, a high-level signal is sent to the installation bus 18 in the unit of the second register.

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corresponding to the addresses of the parallel polled channels, through the converters, 3 codes and groups of logic elements are fed to the control - through the inputs of analog switches.

In the polling polling mode, m channels can be sent to one of the outputs 10 and 11 on the information bus 13 of the second register, a high level signal should be sent overlapping the hp clock pulses, and a signal of the same duration but low level should be sent to the information tick 12 of the first register if polling is carried out on a period: - / output3-10, or a high level signal, if polling is carried out on the second output 11

Thus, by introducing additional elements into the multichannel switchboard, 5, by selecting the appropriate; .1 sequential combinations of control signals that arrive in both registers synchronously via independent-to-independent information buses, carry out simultaneous op-:; J off 5 and 5 as well as shunting and unpredictable channels; those. to implement; chog-5 binded control of analog-:;; pn-: to keys, which is especially necessary for the primary processing of analog-signaling when interrogating matrix solid-state photodetector devices, as it allows by means of disconnecting channels from other channels - g / sgkhkkh to the one opposed, much yy. to introduce the amount of noise interference occurring on high-impedance sensors of photodetectors; TP, and after-); switching off on both / other channels out there - leсdcurrent leaks of preprocessing blocks of analog signals. This cumulative effect leads to an increase in the effective threshold sensitivity and the improvement in the resolving ability of the matrix solid-state photocontrollers, and, consequently, an increase in the accuracy of the multichannel fault-and-distribution systems and the distribution of the data as a whole.

F o r k u l a

the invention

Claims (1)

1. A multi-channel switch containing a caddy switch device consisting of the first and second analog keys in each channel, respectively, the first is a discharge shift register with parallel reading of all bits and a channel sampler with a bus bar, signal inputs Both analog switches of each channel are combined and connected to the input bus of the same channel, the combined outputs of all the first analog switches are connected to the first output bus, and the combined outputs of all the second analog switches to the second output a switch bus, characterized in that, in order to expand its functionality, a second shift register is inserted into it, and the channel sampling device contains both code converters and h groups of logic elements, the first and inverse outputs of the first shift register are connected in each bit with the first and second inputs of the code converter of the same name, and the direct and inverse outputs of the same bit of the second shift register are connected respectively to the third and fourth inputs of the same converter yes, the direct output of the same shift of the second shift register is connected to the first input of the first element AND of the corresponding channel, the second input of which is connected to the reverse inputs of the second and third elements AND of all channels and connected to the inhibit bus, the first and second outputs of the code converter in k; d; each of the canapes is connected to the direct inputs of the second and third elements of the same channel, respectively; the key of the corresponding channel, and the control input of the second analog key is connected to the output of the third And element of the corresponding channel. 2, the switch according to claim 1, characterized in that each of the code converters also contains five h-channel and two R-channel MOS transistors, the drain of the first h-channel MDP transistor is combined with the drains of the second n-channel and first R-channel MDP transistors and connected to the first the output of the code converter, the gates of the first h-and P-channel MOS transistors are combined with the sources of the second P-channel and third n-channel MOS transistors and connected to the first input of the code converter, the source of the first and-channel MOS transistor is connected to the drain of the fourth h-channel MOS transistor, the source of which is connected to the second input of the code converter, the gates of the third and fourth h-channel VDP transistors are combined with the source of the first p-channel MOS transistor and connected to the third input of the code converter, the gates of the second p-channel and the second and n Too-Channel MOSFET Transistors Combined and connected to the fourth input the code converter, the drains of the third and fifth h-channel and second p-channel MOS transistors are connected to the second input of the code converter, the sources of the second and fifth h-channel MOS transistors are connected to the common bus. Editor O. Bugir  Compiled by B. Lementuyev Tehred 0. Sopke Proofreader A. Zimokosov 1332/60 Circulation 816 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35 .. Raushsk nab., d, 4/5 Branch PPP Patent, Uzhgorod, st. Project, 4