SU1211752A1 - Multichannel device for fast fourier transform with pipeline processing of operators - Google Patents

Description

and connected to the overflow output of the second operand counter, the counting input of which is connected to the first input of the first element OR NOT and connected to the inverse output of the first trigger, the direct output of which is connected to the first input of the second element OR NOT, the second input of which is connected to the second the input of the first element SHS-NOT and connected to the output of the OR element, the first and second inputs of which are connected respectively to the low-order output of the first iteration register and the information output of the first operand counter, the overflow output which is connected to the counting input of the third trigger and the input of the third element And, the output of which is connected to the clock input of the first register of iterations, the information output of which is connected to the first input of the first block of elements And, the first information input of the third block of switches and the information input of the first switch, the output of which is connected to the inverse of the input of the third element And and D - the input of the third trigger, the direct output of which is applied to the first input of the first element, and the outputs of the first and second element in And connected to the second

The invention relates to automation and computing, in particular, to devices for implementing fast Fourier transform (FFT), and can be used to solve problems of multichannel spectral correlation processing of sequences of valid samples.

The purpose of the invention is to increase speed.

FIG. 1 is a functional diagram of a multichannel fast Fourier transform device with pipelining of operands.

The device contains a block of 1 fixed memory, an arithmetic unit (AB) 2, memory blocks 3 and 4, an iteration counter 5, a shift block 6, blocks

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the inputs of the first and second blocks of the And elements, respectively, whose outputs are connected to the control inputs of the first and second inverse code calculation nodes, respectively; the output of the first inverse code calculation node is connected to the first information input of the third switch block; the KOTOpioro output is connected to the first information inputs of the first and the second blocks of switches, the outputs of which are connected to the address inputs of the first and second memory blocks, respectively, the access inputs of which are connected to the outputs of the corresponding About the first and second elements OR-NOT, the second information inputs of the first and second switch units are connected to the output of the fourth switch unit, the control input of which is connected to the second inputs of the first and second elements AND, controlling the input of the third switch unit and connected to the forward output the first trigger, the direct output of the second trigger is connected to the control inputs of the first and second switch units, and the information output of the iteration counter is connected to the control input of the shift block.

switches 7-10, nodes 11 and 12 of the calculation of the inverse code, triggers 13 and 14, switches 15 and 16, blocks 17 and 18 of the elements AND, iteration registers 19 and 20 counters of operands 21 and 22, element 11 and 23, elements ШШ-НЕ 24 and 25, elements and 26-28, element SHSh 29, synchronization node 30, triggers 31-32.

The volume of each of blocks 3 and 4 (operative) memory is 2M K-M cells, where K 2 (k 1, 2, .4.) Is the number of input valid sequences; (, 2, ...) is the number of samples of the sequence; К / 2 1 2 (g О, 1, 2,, ..) is the number of complex arrays processed.

The block size of 1 constant memory is N / 2 storage cells of exponential coefficients.

Multichannel device Fast Fourier Transform with pipeline processing of operands works as follows.

In the first 3 and second 4 blocks, 2 K complex arrays of M samples are stored (each array is formed from two valid sequences fa, 5 and,

so refx; aiV, Dm {x;

Gb; 1, the samples inside the arrays are arranged in binary inverse order, the arrays are listed in blocks 3 and 4 also in binary inverse order.

At the input X1 of the device, a binary code is set of the number of processed arrays of one block 3 or 4.

In the initial state, the first 19, second 20 registers of iterations, iteration counter 5, first 31, second 32, third 13 and fourth 14 triggers first 21 operand counters are zeroed and bits of the second 22 operand counters are set to logical 1.

 Synchronization node 30 generates a series of clock pulses arriving at the counting input of the first trigger 31. At the output of the first trigger 31 and the bits of the first 21 and second 22 counters, the source code of the addresses to the first and second blocks 3 and 4 is formed. On the forward and inverse the outputs of the second flip-flop 32 generate the read-write information for the first block 3 and the write-read signal for the second block 4. In addition, the signal from the direct output of the second flip-flop 32 is control for the first 7 and second 8 switch blocks Hur, wherein the signal G on unto {passages. the switches of blocks 7 and 8 of the ps is with information from the first inputs, and by signal 1 from the second inputs. The signals from the overflow outputs of the first 21 and second 22 operand counters through the third 27 and quarter 28

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elements And arrive at the clock inputs of the first 19 and second 20 registers of iterations, respectively. At. this information, stored in the register pax 19 and 20, is shifted by one

bit in the direction of the higher bits, and in the lower bit is entered 1. The state of the bits of the registers 19 and 20 iterations controls the switches

10 corresponding blocks 9 and 10 of switches, so that at their outputs address codes are written during the writing and reading of operands of the first and second blocks 3 and 4 for execution

15 iterations of FFT.

The signal from the overflow output of the second counter 22 of the oranges is fed to the clock input of the counter 5 iterations, the binary code at the outputs of the bits of which controls the shift of the source code received at the information input of the shift unit 6 from the outputs of the node elements 12. Shifted source code at the output of the shift unit 6 is the address of the exponential multiplier W, which is stored in block 1. The sine and cosine values, which are the imaginary and real parts of the exponent W, are received at the input of the AB 2 exponents and stored in the sine and cosine registers АБ-2; At the information input of operands АБ 2 and time interval Т, samples from the first

block 3 (at the input of the write-read control of the first block 3, the potential is O, and the second operand B is first considered. the second operand A; and B). Samples of operands A and B are stored: in the input registers of operands AB 2, B the next time interval T operands A and B are subjected to an elementary transformation of the form AiB W, into input registers

the operands are inserted into the sample C, p from the second block 4, and the value of the sine and cosine registers AB 2 is the value of W. In the time interval T, the converted operands A and B enter the output registers of the AB 2 and are written into the second block 4 (in this case the potential 1 is written at its input to the write-read control input), the operands C and D undergo an elementary transformation, and the input registers of the AB operands 2 introduces samples E and F from the first block 3. In the time interval TC, the transformed operands C and

D is deposited in the first block 3, orfepaHflbi E and f are transformed, and from the second block are read and fed into the input registers AB 2 operands T, H, and the following values are entered into the sine and cosine registers AB 2

exhibitors

relevant

an elementary transformation over the next pair of operands according to the FFT graph with substitution, binary-inverse order of samples at the input and decimation by time.

The table shows the addresses of addresses to the first and second blocks 3 and 4, block 1 and the sequence of processed arrays of 16 complex samples each time.

When the last fn-th FFT iteration is performed, the outputs (n1-1) -th bits of the first 19 and second 20 registers of iterations are set to 1, which through the (K + 1) -th inputs of the first 15 and second 16 switches goes to the information inputs of the third 13 and fourth 14 triggers and blocks the inputs of the first 19 and second 20 registers of iterations. The overflow signals from the outputs of the first 21 liters of the second 22 counters of the operands flip triggers 13 and 14 to the logical 1 state and an additional iteration of the unpacking of the arrays begins. In this case, the signal 1 i

permits the passage of a series of pulses from the output of the first trigger 31 to the second inputs of elements And blocks 17 and 18. A series of pulses through

the first B (, 2, ..., t-1) elements of blocks 17 and 18 pass to the first control inputs of the elements of the first 11 and second 12 nodes and invert the source code of the first bits of the first 21 and second 22 operand counters (the inverting Signal 1 at the output of the first 31 flip-flop during the formation of the address code of the second operand of a pair of operands A and B). The signals from the outputs of the bits (t, 1, ..., p-2, c-1) of the counters 21 and 22 are not inverted, since the zero state of the bits (t, t

+ 1, ..., p-2, and -1) of the first 19 and second 20 registers of iterations block elements (Im, m + 1, ..., n -2, n-1) of blocks 17 and 18, from the outputs which on the control inputs of the corresponding elements of nodes 11 and 12 also receive a signal O. Address codes for the first and second blocks 3 and 4 when executing the decompression are shown in the table. The signal 1 from the output of the fourth trigger 14 is fed to the second control input of AB 2, which performs an elementary type conversion.

The IL 29 element, the first 24 and second 25 OR-NOT elements are designed to generate signals that the first and second blocks 3 and 4 will not access when writing information from / to zero the output registers of AB 2 to blocks 3 and 4 in place of the first pair of operands during the execution of the first FFT iterations.

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 ABOUT

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Compiled by A. Baranov Editor T. Parfenova Tehred A. Babinets Corrector L. Patay

Order 642/54

Circulation 673

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Branch ShSh Patent, Uzhgorod, st. Project, 4

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Claims (1)

MULTI-CHANNEL DEVICE FOR FAST FOURIER TRANSFORM WITH CONVEYOR PROCESSING OF OPERANDS, containing a permanent memory block, the output of which is connected to the input of the coefficients of the arithmetic block, the information output of which is connected to the information inputs of the first and second memory blocks, the outputs of which are connected to the input of the operands of the arithmetic block, the synchronization input of which is connected to the first output of the synchronization unit the second output of which is connected to the counting input of the first trigger, the direct output of which is connected to the counting input of the second trigger, the direct output of which connected to the input of the control "record - reading the first memory block and the first counter count input operands, information output of which is connected to the information input unit for inverse code inverse output of the second flip-flop to the input of Con chen-recording schi- control. by reading the second memory block, the first iteration register, characterized in that, in order to improve performance, the first, second, third and fourth switch blocks, a shift block, an iteration counter, a second inverse code calculation unit, the first and second elements OR are introduced into it NOT, OR element, first and second blocks of AND elements, first and second switches, third and fourth triggers, second iteration register and second operand counter, the information output of which is connected to the information input of the second inverse computing node an ode whose output is connected to the first information input of the fourth block of switches and information. the shift block input, the output of which is connected to the address input of the read-only memory block, the access input of which is connected to the input, synchronize the reception of the arithmetic block coefficients, the first input of the second AND element, and is connected to the direct output of the fourth trigger, whose D input is connected to the inverse input the fourth element And is connected to the output of the second switch, the information input of which is connected to the first input of the second block of elements And, the second information input of the fourth block of switches and> connected to the output of the second iteration register, the clock input of which is connected to the output of the fourth AND element, the input of which is connected to the counting input of the fourth trigger, the counting input of the iteration counter and connected to the overflow output of the second operand counter, the counting input of which is connected to the first input of the first element OR -HE and is connected to the inverse output of the first trigger, the direct output of which is connected to the first input of the second OR-HE element, the second input of which is connected to the second input of the first OR-HE element and connected to the output of the OR element, the first and second inputs of which are connected respectively to the low-order output of the first iteration register and the information output of the first operand counter, the overflow output of which is connected to the counting input of the third trigger and the input of the third AND element, the output of which is connected to the clock input of the first iteration register the information output of which is connected to the first input of the first block of AND elements, the first information input of the third block of switches and the information input of the first comm an amplifier whose output is connected to the inverse input of the third AND element and the D-input of the third trigger, the direct output of which is connected to the first input of the first AND element, the outputs of the first and second AND elements are connected to the second. 1211752 · inputs of the first and second blocks of AND elements, respectively, the outputs that are connected to the control inputs of the first and second nodes of the inverse code calculation, the output of the first node of the inverse code calculation is connected to the first information input of the third block of switches, the output of which is connected to the first information inputs of the first and the second switch blocks, the outputs of which are connected to the address inputs of the first and second memory blocks, respectively, whose access inputs are connected to the outputs, respectively As regards the first and second elements of OR-HE, the second information inputs of the first and second blocks of switches are connected to the output of the fourth block of switches, the control input of which is connected to the second inputs of the first and second elements of AND, the control input of the third block of switches and is connected to the direct output of the first trigger, the direct output of the second trigger is connected to the control inputs of the first and second switch blocks, and the information output of the iteration counter is connected to the control input of the shift block.