SU1205084A1 - Apparatus for testing parameters of complex systems - Google Patents

Description

3. The device according to claim 1, characterized in that the mode block contains the first element NOT connected to the input to the input of the mode block and to the disconnecting contact of the switch, the switching contact of which is connected to the output of the mode block, and the closing contact to the output of the first item NOT

4. The device according to claim 1, characterized in that the reference signal block comprises first and second voltage dividers connected by first pins to the power supply bus of the device, second pins to the common bus of the device, third pins to the first

and the second outputs of the reference signal unit, connected respectively via the first and second voltmeters to the common bus of the device,

5. The device according to claim 1, characterized in that the decryption unit contains the first and second decoders connected by inputs with information inputs of the decryption unit, gating inputs with the gating input of the decryption unit, the outputs of the first decoder are connected with the corresponding; the outputs of the decryption unit, the outputs of the second decoder are connected via the second elements NOT to the corresponding outputs of the decryption unit.

The invention relates to instrumentation technology and can be used for tolerance monitoring of object parameters.

The purpose of the invention is to expand the functional capabilities of the device by providing a tolerance control of several parameters and controlling the total number of parameters that have gone beyond the tolerance with an operably variable value of the range of permissible values.

Fig, 1 shows a block diagram of the proposed device; FIG. 2, QxeMa comparison block; Fig, 3 - Sche05084

6. A device according to claim 1, characterized in that the synchronizer comprises a pulse generator connected with the output to the first output of the synchronizer and with a counting input nepBoi o counter connected to the outputs with the second outputs of the synchronizer.

7. The device according to claim 1, 1, of which the logical block contains the first element I connected by inputs to the second inputs of the logical block connected directly by the first input to the first input of the second element I through the third element NOT to the first output of the logic unit and to the first input of the third element I connected to the output of the second output of the logic unit, the second input to the output of the first element I and to the second input of the second element I connected to the output of the third output of the logic unit

8. The device according to claim 1, characterized in that the integral evaluation unit contains the fourth element I, connected by the first and second inputs with the same

I inputs of the integral evaluation unit, output - with the counting input of the second counter, connected by the outputs from output 1 and the integral evaluation unit, the installation input - with the third input of the integral evaluation unit.

ma mode block; Fig, 4 is a block diagram of the reference signals; FIG. 5 is a diagram of a decryption unit; Fig, 6 is a diagram of the synchronizer; figure 7 - diagram of the logic unit; Fig, 8 is a block diagram of the integrated assessment.

The device contains a switch 1, block 2 comparison, block 3 mode,

a reference signal unit 4, a decryption unit 5, a synchronizer 6, a logic unit 7, an integral evaluation unit 8, a memory unit 9, an integral evaluation indication unit 10 and a matrix display unit 11.

Comparison unit 2 comprises a comparator 12, a first 13, a second 14, a sixth 15, a fifth 16, a seventh 17, an eighth 18, a third 19, and a fourth 20 resistors.

The mode block 3 comprises the first element HE 21 and the switch 22.

The reference signal block 4 contains the first 23 and second 24 voltage dividers and the second 25 and first 26 voltmeters.

J Block 5 decryption contains the first 27 and second 28 decoders and the second elements are NOT 29.

The synchronizer 6 contains a pulse generator 30 and the first counter 3

Logic block 7 contains the first element And 32, the third element is NOT 33, the second is 34 and the third is 35 elements I.

Block 8 of the integral evaluation contains the fourth 36 element And the second counter 37,

The switch 1 is made, for example, on chips K590KN1.

In block 2 of comparison, comparator 12 is made, for example, on a 52fCA1 chip.

Memory block 9 is built, for example, on a register of D-flip-flops having C and D inputs.

Block 10 indication of the integral evaluation is performed, for example, on digital indicators ALS324B, each of which is equipped with a decoder K314ID2 at the input.

Switch 1 is connected by information inputs to the corresponding inputs of the device, and the output is connected to the first input of comparison unit 2 connected by the second and third inputs to the first and BTop bw outputs of the reference signal block 4, and output through the block 3 of the mode to the gate input of the block 5 decoding and with the first input of the block 8 1 integrated, connected by the second and third inputs respectively to the first and second outputs of the logic unit 7 connected by the first input to the first output of the synchronizer 6, the second inputs to the second outputs synchronizer 6, with the control inputs of the switch 1 and with information decryption unit 5 inputs connected with respective outputs of the matrix display input section 11. The input of the integral evaluation indication unit 10 is connected to the output of the memory unit 9 connected by information inputs to the outputs of the integral evaluation unit 8, strobe

input - with the third output of logic block 7.

In unit 2 of the comparison, the first resistor 13 is connected to the first output of the common bus device, the second output - with the first non-inverting input of the comparator and the first output of the second resistor 14 connected with the second output to the first input of the comparison unit 2, and

the third resistor 19 with the second inverting input of the comparator 12 and with the first output of the fourth resistor 20 connected with the second output with the second input of the comparison unit 2 directly, and through the fifth resistor 16 with the first inverting input of the comparator 12 and with the first output of the sixth resistor 15 connected by the second output to the third input

Comparison unit 2 and the first output of the seventh resistor 17, connected by the second output via the eighth resistor 18 to the common bus of the device, and directly to the second non-inverted input of the comparator 12, connected to the output of the output of the comparison unit 2.

in block 3 of the mode the first element is NOT 21 connected to the input of the block

3 modes and with the break contact of the switch 22, the switching contact of which is connected to the output of the mode block 3, and the closing contact with the output of the first element

NOT 21.

In block 4 of the reference signals, the first 23 and second 24 voltage dividers are connected by the first terminals of the device power bus, the second

pins - with a common bus device, the third pins - respectively with the first and second outputs of the block 4 reference signals connected respectively through the first 26 and second

25 voltmeters with a common bus device.

In block 5 decryption, the first 27 and second 28 decoders are connected by inputs with information inputs

gating unit 5, gating inputs with gating input of decoding unit 5, the outputs of the first decoder 27 are connected to the corresponding outputs of the decoding unit 5, and the outputs of the second decoder 28 through the second elements NO 29 - with the corresponding outputs of the decryption unit 5.

In the synchronizer 6, the pulse generator 30 is connected by an output to the first output of the synchronizer 6 and to the counting input of the first counter 31, which is connected to the outputs of the second outputs of the synchronizer 6.

In logic unit 7, the first element AND 32 is connected by inputs to the second inputs of logical unit 7 connected directly to the first input of the second element AND 34, and through the third element NOT 33 to the first output of logic unit 7 and to the first input of the third element I 35 connected to the second output of the logic unit 7, the second input to the output of the first element 32 and the second input of the second element 34 connected to the third output of the logic unit 7.

In block 8 integral evaluation of the fourth element And 36 is connected to the first and second inputs with the same inputs of block 8 integrated evaluation, output - with the counting input of the second counter 37 connected to the outputs of the outputs of block 8 integrated assessment, the installation input to the third input of the integral evaluation.

The device works as follows.

Subject to control parameters, for example, (temperature, humidity, etc., in controlled points distributed in space. It is required to determine whether the current value of V | j parameters is within the specified tolerance limits Vg-V: YX VQ + У ", then EO is the average value of the parameter Vf, - the absolute allowable value of the parameter deviation from the average value (Fig. 2b). Each controlled point is characterized, for example, by the spatial coordinate and values of several parameters. The values of the parameters in each of the controlled points are converted into an electric signal, and normalizuyuts receives inputs from the device to the switch inputs .. The switch 1 1 is controlled by a generator 30

pulses and a counter 31 included in the synchronizer 6 (Fig. 6). The time-increasing binary codes arrive from the outputs of the synchronizer 6 5 to the inputs of switch 1 and control the time-sequential connection of signals from monitored points through switch 1 to the input of comparator 2 to check for

0 parameter in the admission. The signals from the outputs of the counter 31 in the synchronizer 6 also arrive at the information inputs of the decoders 27 and 28 of the decryption unit 5 (figure 5) and provide

5, the selection of the indicator in the matrix block 11 of the display by two coordinates, the first of which (for example, the number of the controlled point) is determined by the decoder 27, and the second (for example,

0 parameter type) - a decoder 28 and elements NOT 29.

If there is a level of logical units on the strobing inputs of the decoders 5 and 27 and 28 coming from the output of block 3 of the mode, the indicator selected with the help of the decoders 27 and 28 is turned on in the matrix unit 11 and EZdication, and if there is a level of logical zero, the corresponding indicator does not light up . The value of the logic level at the gate inputs of the baffles 27 and 28 is determined by the position of the switch 22 in the block 3 modes and the output state of the block 2 of the comparison (Fig. 3). When the input of block 3 is directly connected with its output and there is a logic unit level at the output of the comparison block 2, the corresponding indicator in the matrix display unit 11 lights up, and if there is a logic zero level, it does not light up.

Comparison unit 2 (Fig. 2) performs a double-threshold tolerance control of finding the value of a parameter arriving at its first input from the output of switch 1 in case the parameter is in tolerance, the output of the comparison unit 2 produces a logical zero signal, if not logical unit. The values of V and V for setting them to the comparison unit 2 are formed in the 4 reference signal unit (Fig. 4). 5 The values of V are set by the operator using a voltage divider 24 as indicated by a voltmeter 25 and are fed to the connection point of the resistors.

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15 and 17 in block 2, and the values of Vp are set by the operator using a voltage divider 23 and a voltmeter 26 and are fed to the connection point of resistors 16 and 20 in block 2 of the comparison.

As a result, with the position of the switch 22 shown in FIG. 3, the display unit 11 includes all indicators corresponding to the various controlled points and their parameters that are outside the tolerance limits. Since the survey points are controlled cyclically, each of the indicators in block 11 blinks, but by selecting the frequency of the generator 30 large enough, you can make this blink invisible to the human eye.

Changing the values of V (j and V | with the help of dividers 23 and 24, i.e. actually changing the tolerances for the parameter deviation from the norm, you can quickly determine the parameters of spatially distributed points that are within the specified tolerance and which are absent, i.e., to evaluate the state of the object as a whole.

In the case of switching, the switch 22 in block 3, the signal from the input of block 3 passes to its output through inverter 21, which leads to the inversion of the display in block 11. At that, the indicators of block 11, corresponding to the controlled points, whose parameters are in tolerance, and Indicators corresponding to unsuitable controlled points are not hot.

Simultaneously with the display of numbers of unsuitable monitored points and parameters, the device counts the number of monitored points in which the parameter is out of tolerance. For this, the clock pulses from the generator 30 in the synchronizer 6 arrive at the input of the element HE 33 in block 7 and then to one input of the element 36 in the block 8 of the integral evaluation (Fig. 8). Through the element 36, the sync pulses are passed to the input of the counter 37 only if there is a high level at the other input of the element 36, which is formed when the parameter of the controlled point is outside the tolerance (in the switch position shown in FIG.

bodies 22) or when the parameter is within the tolerance (when switching switch 22 from the initial position). As a result, the counter 37 counts the number of controllable points whose parameters are within the tolerance (or outside the tolerance). At the end of the next cycle of filling the counter 31 in the synchronizer 6, after polling all

10 types of device by the switch 1, the counter 31 forms the end-of-cycle code, which is allocated by the element AND 32 in logic block 7 (FIG. 7), the last high from its level

The 15th output allows the clock to pass from the generator 30 through the elements 34 and 35. On the leading edge of the clock from the output of the element 34, a recording gate is output.

20 to block 9 of memory, and on its falling front through element 35, counter 37 in the block is reset.

which the

Prepares for the next work cycle.

The contents of memory block 9 are indicated by display unit 10, by the indications of which it is possible to determine the number of points whose parameters are out of tolerance (or in tolerance). Changing the values of V and V with the help of dividers 23 and 24 in block 4, you can quickly track the change in the number of controlled points with parameters in a given tolerance and thus assess the state of the control object as a whole.

Comparison unit 2 (FIG. 2c |) performs two-threshold control of the input signal to the point of resistors 14 and 19. Resistors 13 and 18 provide for dividing the signal V and the value V for setting them to the inputs of the two-threshold comparator 12. With the help of resistors 15 and 16, at the first inverting input of the comparator 12, a signal is generated that is proportional to the value of Vg -t- V, which is compared to a signal proportional to V,

coming from the divider resistors 14 and 13 to the first inverting input of the comparator 12. Resistors 19 and 20 produce a signal proportional to Vy-V at the second inverting input of the comparator 12, which is compared with the signal proportional to V generated by the second non-inverting

the input of the comparator 12 V, - V Vy- (Vo + V ,,).

If the Chu parameter is in the tolerance, the comparator 12 produces a logic zero level at the output,

As a result of cyclic polling of all control points of the object under study in the matrix display unit 11 ,,; exhaustive data about its state are displayed, for example, presented in the form of a multi-layer mnemonic scheme in the form of an object block diagram, on which data about the modes of the blocks is highlighted in one color, and the parameters of the signals in a different color. At the same time, the display unit 10 displays the results in arbitrary points characterizing the controlled object as a whole.

In medicine, the device is suitable for a comprehensive study of the state of the human body according to a given type of parameters. In this case, the images of a person in which the indicators are located in the same way as the sensors on the patient's body are displayed on a multi-layered mimic, depicting the distribution of this parameter over the patient's body,

In agricultural engineering, the device can be used to monitor the state of air and soil (temperature, humidity) in greenhouses, and the intensity of illumination in them.

In meteorology, the device allows you to automatically display

0 isotherms, isobars, etc. selected district, region, province.

Similarly, the device can be used to monitor the state of machines, apparatus,

5 dams, bridges, chemical equipment and many other objects.

Thus, the proposed device provides research and integrated control.

0 states of technical and natural objects, namely, determining the address of control points with specified positive or negative properties, promptly changing the tolerance limits within wide limits and determining the distribution of parameter values in the controlled object, as well as measuring the number of control points with a given property and characterizing the quality of the controlled object as a whole, which expands its functionality.

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Claims (8)

1. DEVICE FOR MONITORING THE PARAMETERS OF COMPLEX SYSTEMS, comprising a matrix display unit, an integral evaluation unit and a switch connected by information inputs to the corresponding inputs of the device, characterized in that, in order to expand the functionality of the device by providing tolerance control of several parameters and controlling the number of parameters, out of tolerance with an operatively variable value of the region of admissible values, a synchronizer, a logical block, a comparison block, a p block are introduced into it a presser, a decryption unit, an integral assessment indication unit, a reference signal unit, a memory unit, the output of the switch being connected to the first input of the comparison unit connected to the second and third inputs, respectively, with the first and second outputs of the reference signal unit, the output through the mode unit with a gating input decryption unit and with the first input of the integrated evaluation unit, connected by the second and third inputs, respectively, with the first and second outputs of the logical unit, connected by the first input with the first output of the synchronizer, W inputs - with the second outputs of the synchronizer, with the control inputs of the switch and with the information inputs of the decryption unit, connected by the outputs to the corresponding inputs of the matrix display unit, the input of the integrated evaluation unit is connected to the output of the memory unit connected by the information inputs with the outputs of the integrated unit, gating input - with the third output of the logic block. 2. Device according π.1, l and m of h and w · _β o f e c i in that the comparator unit comprises a first resistor, a first terminal coupled to the common bus device, the second terminal - a first non-inverting input of the comparator and to the first the output of the second resistor connected directly by the second output to the first input of the comparison unit, and through the third resistor to the second inverting input of the comparator and the first output of the fourth resistor connected directly by the second output to the second input of the comparison unit, and through the fifth resistor to the first with the rubbing input of the comparator and with the first output of the sixth resistor connected to the third input of the comparison unit and the first output of the seventh resistor connected to the second terminal through the eighth resistor with the device common bus, and directly to the second non-inverting input of the comparator connected to the output of the unit comparisons. SU „„ 1205084 3. The device according to claim 1, characterized in that the mode block contains the first element NOT connected by the input to the input of the mode block and with the opening contact of the switch, the switching contact of which is connected to the output of the mode block, and the making contact is with the output of the first item NOT. 4. The device according to claim 1, characterized in that the reference signal block comprises first and second voltage dividers connected by the first terminals to the device power bus, the second terminals to the device common bus, and the third conclusions respectively to the first and second outputs of the block reference signals connected respectively through the first and second voltmeters with a common bus device. 5. The device according to claim 1, with the fact that the decryption unit contains the first and second decoders connected by inputs to the information inputs of the decryption unit, gate inputs - with the gate input of the decryption unit, outputs the first decoder is connected to the corresponding outputs of the decryption unit, the outputs of the second decoder are connected through the second elements NOT to the corresponding outputs of the decryption unit. 6. The device according to claim 1, characterized in that the synchronizer comprises a pulse generator connected by the output to the first output of the synchronizer and to the counting input of the first counter connected to the outputs of the second outputs of the synchronizer. 7. The device according to claim 1, including the fact that the logical unit contains the first element And connected to the inputs of the second inputs of the logical unit connected by the first input to the first input of the second element And directly, and through the third element NOT with the first output of the logical unit and with the first input of the third element And connected to the output with the second output of the logical unit, the second input with the output of the first element And with the second input of the second element And connected to the third output of the logical unit . 8. The device according to claim 1, characterized in that the integrated assessment unit contains a fourth element And connected by the first -and the second inputs with the same inputs of the integrated evaluation unit, the output - with the counting input of the second counter connected by the outputs to the outputs of the integrated evaluation unit, the installation input - with the third input of the integrated evaluation unit.