SU1200418A1 - Displacement-to-digital converter - Google Patents

Abstract

1. A TRAVEL TRANSMITTER TO A CODE containing an illuminator optically connected through aperture holes made in increments, holes in the Vernier code element made in steps a, a (0.25), where k is a positive integer and the first and second keys the photodetectors, the output of the first photodetector is connected to the input of the voltage converter in the code, the output of the second photodetector is connected to the input of the control signal generator, the output of which is connected to the first input of the first subtraction unit, a permanent storage device The device whose outputs are connected to the first group of inputs of the first subtraction unit, whose outputs are the transducer outputs, characterized in that, in order to increase the accuracy of the converter, a write pulse shaper, a random access memory, second and third subtraction blocks, and outputs are entered into it. the voltage converter into the code is connected to the first groups of inputs of the second and third subtraction units; the outputs of the third subtraction unit are connected to the second group — the inputs of the first subtraction unit; the outputs are the memory device is connected to the second group of inputs of the second subtraction unit, the inputs of which are connected to the group of inputs of the operational memory device whose outputs are connected to the second group of inputs of the third subtraction unit, the output of the control signaling device i is connected to the input of the control signal .no random access memory. 2, the converter according to claim 1, wherein the second subtraction unit comprises two groups of inverters and an adder, the inputs of the first group of inverters are the first group of inputs of the block, the outputs of the first group of inverters are connected to the first group of inputs of the adder, the second group of inputs of which The second group of inputs of the same name of the block, the outputs of the adder are connected to the inputs of the second group of inverters, the outputs of which are the outputs of the block, 3. The converter according to claim 1, which is the fact that the third subtractor contains the adder. and the group of inverters, the first and second group of inputs of the adder are the corresponding groups of inputs of the block, the outputs of the adder are connected to the inputs of the group of inverters, the outputs of which are the outputs of the block.

Description

4. The converter according to claim 1, wherein the random access memory is made on D-flip-flops, the information inputs of which form a group of device inputs, and the synchronization inputs are combined and are the control input of the device, the inverter outputs of D-flip-flops are outputs devices.

5. The converter according to claim 1, characterized in that the write pulse driver contains three inverters connected in series and an NAND element, the input of the first inverter is connected to the first input of the NAND element and is the input of the former, the output of the last inverter is connected to the second input element AND IS, the output of which is the output of the former.

The invention relates to automation and computing and can be used as converters of mechanical movements in a digital code.

The purpose of the invention is to increase the accuracy of the converter.

Fig. 1 shows the functional diagram of the displacement transducer to the code in Fig. 2, block diagrams. blocks of readout of the operational memory of the device and the driver of the pulses of recording and connecting these blocks with other blocks of the converter; in Fig. 3, the dependences of the signals caused by the error of the voltage converter in the code are shown in the converter as a function of the transformed movement of the dotted line. 20

The displacement transducer to the code (FIG. 1) contains input shaft 1, diaphragm 2, vernier code element 3, loops 4, photoreceiver 5, shaper 6 control signals, a simple memory (ROM 7, voltage converter 8 code ( PNK |, blocks 9-11 readout, random access memory (RAM) 12, shaper J3 write pulses, subtraction unit 10 contains a block of 14 inverters, an adder 15 and a block 16 of inverters, subtracting unit 11 contains a adder I7 and a block 18 inverters, operative storage device 12 contains a block 19 D-flip-flops, and the driver of the 13 write pulses - the inverters 20-22 and the element Y-NE 23,

The motion to code converter operates as follows.

During the rotation of the input shaft 1 with diaphragm 2, the optical signals at the outputs of the vernier code element 3 change from zero to the maximum value according to a triangular law with a period of 01. The spatial phase shift between the optical signals fed (through the focons 4) to the photodetectors 5, is: a quarter of the period, t, e, QO / photoreceivers 5, produce electrical signals proportional to the optical signals at the output of the nonnusable code element 3 (Fig. 3a). The signal from the output of one of the photodetectors 5 is fed to the input of the NCP B, which operates, for example, in binary code. When the signal changes from zero to a maximum, the output of the OCP 8 increases the output code values. In this case, the maximum value of the signal at the output of PNK 8 (FIG. 3b) corresponds to the maximum value of the signal at the PNA B input. The resolution of the PCN 8 output code is conventionally not shown, since the code increments corresponding to the low-order bit are small. The output code from PKN 8 goes to block II subtraction, where the output code of RAM 12 is subtracted from the output code of PACE 8, the Output code of RAM 12 is equal to the additive error of PNK 8, the Output code of block 11 of subtraction is fed to the input of block 9 of subtraction, where the output is formed Motion Converter to Code,. Single-movement detection using PKN 8 occurs only in the first half of step a. For an unambiguous reference to everything. The period of the opsh scale q uses a signal from another photodetector 5. This signal enters the shaper 6 of the control of each signal, where the formation of a signal of a rectangular formula (Fig. 38) from it occurs. A change in the polarity of the control signal occurs at those moments when the signal from the photodetector 5, connected to the NCP 8, has a maximum or minimum value. The signal from the driver 6 of the control signal controls the operation of the block. 9 subtraction. When changing the code and the output of the OSP 8 from the minimum p, the maximum value of the subtractor 9 by the control signal shaper 6 passes the output code of the subtraction unit 11 to the output without changing, and when crossing the ambiguity boundary, i.e. through, in subtraction unit 9, an operation is subtracted from the code recorded in the ROM 7j of the output code of subtraction unit 11. The value of the code recorded in ROM 7. is twice as large as the maximum code value at the output of the NCP 8. As a result, at the output of block 9, when the shaft 1 turns from zero to a, the code uniquely increases from zero to maximum, equal to the value of the code recorded in the ROM 7. The dependence of the output code of the subtraction unit 9 on the transformed movement in the absence of additive fault Pnk 8 is shown in FIG. 3 solid line. The additive error of the OCP 8 causes the OCP 8 output code to be shifted by the magnitude of the absolute error, as shown by the dotted lines in FIG. 3. The presence of the additive error of the NCP 8 may cause the output code to be generated with an error, as shown in FIG. 3 by the dotted line. Moreover, the sign of the error changes when crossing the ambiguity boundary, i.e. GO / 2. The additive error of the PNK 8 affects the output code of the converter by the fact that the output code of the PNK 8 gains an increment equal to the absolute value of the additive 18 of the error D. D. This is shown graphically in FIG. 3 dotted line. The consequence of this is the ambiguity of the output code with respect to the movement being converted, as shown in FIG. 3 dotted line. In the displacement transducer to the code, the eliminated effects of the additive error of the OVC 8 on the output transducer code are performed using subtraction blocks 10 and 11, RAM 12 and the writing pulse generator 13. The output codes of PNK 8 and ROM 7 are fed to the inputs of subtraction unit 10, from the output of which a code equal to the difference code of PNK 8 and half of the code of ROM is fed to the input of RAM 12, the code from the output of ROM 7 is fed to the input of block 10 subtraction reduced twice This is achieved by shifting the binary code one bit towards the low bit. This is done by connecting the output bus i-ro bit ROM 7 with the input bus (i-f) bit block 10 subtraction. At the moment when the output code of the OSP 8 reaches its maximum value, the differential output code of the subtraction unit 10 is recorded in RAM 12. The recording is effected by a signal generated by the shaper 13 of write pulses, the input of which is connected to the output of the shaper 6 of the control signal. The code recorded in RAM 12 is equal to the absolute value of the OCP 8 error. This code enters subtraction unit 11, where it is subtracted from OCP code 8. R result, the code proportional to the transformed displacement and not dependent on the input to subtraction unit 9 occurs. The additive error of the NCP 8 (Fig. 3b, a solid line is Y. The consequence of eliminating the influence of the additive error of the NCP 8 is that the unambiguous dependence of the output code on the transformed displacement occurs throughout the whole step of the reference scale a, as shown by a solid oh line in Fig. 3g. The output code of the adder 15 is fed through a block of 16 inverters to the information inputs of RAM 12. The reverse code of the sum of the direct code of one number and the reverse code of another number is equal to the difference of these two numbers.Therefore, to the information inputs of RAM 12 to the post

The code is equal to the spacing of the output codes of the OSP 8 and ROM 7. At the same time, the input buses of the adder 15 are connected to the output buses of the ROM 7 with a shift of one bit towards the lower bit, which ensures that the half value of the output code of the RAM is input to the input of the accumulator 15 7

The control input of the RAM 12 is connected to the output of the driver of the write pulses 13, which forms a short negative pulse (the duration of which is equal to the delay time; the signal in the three inverters 20: -22 ,.

beginning at the moment of occurrence of a positive pulse front at the output of the driver 6 of the control signal.

The outputs of the RAM T2 are connected to the inputs of the adder 17 of the subtracting unit 11. Thus, the input of the adder 17 receives the inverse of the code written in RAM 12, the Output code of the adder 17, is fed to the inverter unit 18, whose transponder code is equal to the difference between the codes of the PNK 8 and RAM 12. This difference code is fed to the input of the subtracting unit 9.

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Claims (5)

1. A TRANSFER FOR MOVING TO A CODE containing a illuminator optically connected through aperture openings made in steps a _Q , openings of a nonius code element made in steps a _n . = = a ₀ (k + 0.25), where k is a positive integer and focons with the first and second photodetectors, the output of the first photodetector is connected to the input of the voltage converter into code, the output of the second photodetector is connected to the input of the control signal generator, the output of which is connected with the first input of the first subtraction unit, read-only memory, the outputs of which are connected to the first group of inputs of the first subtraction unit, the outputs of which are the outputs of the converter, characterized in that, in order to improve the accuracy of the conversion atelier, write pulse generator, random access memory, the second and third subtraction blocks, the outputs of the voltage-to-code converter are connected to the first groups of inputs of the second and third subtraction blocks, the outputs of the third subtraction block are connected to the second group of inputs of the first subtraction block, the outputs of read-only memory are connected to the second group of inputs of the second subtraction unit, the outputs of which are connected to the group of inputs of random access memory, the outputs of which are connected us with a second group of inputs of the third subtracting unit, an output control signa generator la is connected through a pulse shaper to an input of the recording management random access memory. 2. The converter according to π, 1, characterized in that the second subtraction unit contains two groups of inverters and an adder, the inputs of the first group of inverters are the first group of inputs of the unit, the outputs of the first group of inverters are connected to the first group of inputs of the adder, the second group of inputs of which is the second the same group of inputs of the block, the output of the adder connected to the inputs of the second group of inverters, the outputs of which are the outputs of the block, 3. The converter according to π. 1, characterized in that the third block of subtraction contains the adder ·. and a group of inverters, the first and second group of inputs of the adder are the corresponding groups of inputs of the block,. the adder outputs are connected to the inputs of the inverter group, the outputs of which are the outputs of the unit. 4. A converter according to π, 1, characterized in that the random access memory is executed on D-flip-flops, the information inputs of which form a group of inputs of the Device, and the synchronization inputs are combined and are the control input of the device, the inverter outputs of the D-triggers are the outputs of the device. 5. The converter according to π. 1, characterized in that the recording pulse shaper contains three series-connected inverters and an AND-NOT element, the input of the first inverter is connected to the first input of the AND-NOT element and is the input of the shaper, the output of the last inverter is connected to the second input of the AND-NOT element, the output of which is the output of the shaper.