SU1198744A1 - Generator of time intervals - Google Patents

Description

The invention relates to a pulse technique and can be used in automatic devices

and devices for signal synthesis dis-; cretizations. The purpose of the invention is to improve the accuracy of the formation of the time interval due to the gating of the transfer signal of the counter. The device works as follows. When a signal is received from the control bus 9 to the information input of the trigger 1, the latter switches to one state. Writing "1" in the trigger 1 is carried out on the front of the negative synchronization pulses,; coming from the bus 8.

In this case, the passage of counting pulses from the bus 10 to the counting input of the counting pulse 3 is allowed. By filling its capacity, determined by the installation code on the tires 11, the counter 3 generates a transfer signal at the output, which is stabilized by a pulse coming from the tire 8 to the second input of the element 4 NAND, sets the trigger 1, the counter 3, and starts the driver 5 pulses of fixed duration. At the output of the bus 6, a pulse is formed, delayed relative to the front of the pulses removed from the bus 7, and at the output of the trigger 1, respectively, forward and inverse pulses, the duration of which is equal to the pulse delay from the outputs of the driver 5 pulses. At the counting input of the counter 3 pulses, a stack of counting pulses is also formed, the duration of which is equal to the delay of the pulses taken from the output buses

7. It is noted that the highest accuracy is ensured at a frequency of counting pulses equal to or a multiple of the frequency of synchronization pulses. 1 il.

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The invention relates to a pulse technique and can be used in automatic devices'

/ and sampling signal synthesis devices.

The purpose of the invention is to improve the accuracy of the formation of the time interval due to the gating of the transfer signal of the counter.

The drawing shows a functional circuit of a temporary driver. interval.

The shaper of the time interval contains the trigger 1, the first element 2 N – N, the counter of 3 pulses, the second element 4 N – N, the former of 5 pulses, the first group of output buses 6, the second group of output buses 7, the input bus 8 of synchronization, the bus 9 of control, input bus 10 counting pulses, code bus group 11.

The direct output of the trigger 1 is connected to the first input of element 2 AND-NOT, the second input of which is connected to the input bus of the counting pulses, the output of element 2 AND-NOT connected to the counting input of the counter 3 pulses, the transfer output of which is connected to the first input of the second element 4 AND - NOT, the second input of which is connected to the synchronization input bus 8 and the synchronization input of trigger 1, and the output of element 4 is NOT connected to the setup input of trigger 1, to the pre-recording input of counter 3 and to the input of the driver of the 5 pulses, direct and inverse outputs of which о is connected to the corresponding output buses b, and the direct and inverse outputs of the trigger 1 are connected to the corresponding output buses 7, the information input of the trigger 1 is connected to the input bus 9 of the control, the second input of the first element 2 is NOT connected to the input bus 10 of the counting pulses, and information inputs of the presetting of the counter 3 are connected to the corresponding code buses 11.

The device can be implemented, for example: trigger 1 on the chip 155 TV 9, elements 2 and 4 AND-NOT - 155 LAZ, Counter 3 - 155 IE 7, shaper 5 pulses t 155 AG 1.

The device works as follows.

The initial state of trigger 1 is zero. When a signal arrives from shi1198744 '1

9 controls on the information input of the trigger 1, the latter goes into one state. Writing ”1" to trigger 1 is carried out on the front of negative synchronization pulses £ _g coming from bus 8. This allows the counting pulses to pass from the bus 10 to the counting input of the pulse counter 3. The last 10 by filling its capacity; tires 11, generates a transfer signal at the output, which is stabilized by a pulse-pulse coming from bus.8 to the second 5 input of element 4 NAND, and sets trigger 1 to its initial state, counter 3 and starts shaper 5 of fixed-duration pulses. At the same time on the output tires 6 20 an impulse is formed, delayed

with respect to the front of the pulses removed from the bus 7, and at the outputs of the trigger 1, there are, respectively, direct and inverse pulses, the duration of which is equal to the magnitude of the pulse delay from the outputs of the driver of the 5 pulses. At the counting input of the counter 3 pulses, a stack of counting pulses is also formed, the duration of which is equal to GF on the delay of pulses taken from the output tires 7.

The highest accuracy is ensured at a frequency of counting pulses equal to or a multiple of the frequency of synchronization pulses.

Claims (1)

Claim* A time interval former that contains a counter, the first and second NAND elements and a trigger, whose output is connected to the first input of the first NAND element, the output of which is connected to the counter count input, characterized in that, in order to increase the accuracy of forming the time interval in Ebony introduced pulse shaper and counter carry output is connected to the lane · vym input of the second aND-NO element, Tue ⁵⁰ ^ swarm input of which is connected to the synchronization input bus, an output of second aND-NO element is connected to the trigger input of the installation , the input of the pre-recording of the counter and the input ⁵⁵ of the pulse shaper, the direct and inverse outputs of which are connected respectively to the first and second output buses, while the direct and E 1198744 4 the inverse outputs of the trigger are connected respectively to the third and fourth output buses, the information input of the trigger is connected to the input bus of the counting pulses, the second input of the first I-NOT element is connected to the control input bus, and the information inputs of the preliminary recording are connected to the corresponding input code buses.