SU1196949A1 - Storage - Google Patents

Abstract

I. A STORAGE DEVICE containing memory blocks, the first and second inputs and outputs of which are respectively the first and second inputs and the first output of the device, the address blocks whose outputs are connected to the third inputs of the corresponding memory blocks, which is different. Since, in order to increase the capacity of the device, a shaper of address signals, the input of which is connected to the outputs of the memory blocks, is entered into it, the first and second outputs are connected to the first and second inputs of the memory blocks and address blocks, the third and fourth outputs the address generator. The signals and the third and fourth inputs of the address blocks are the third and fourth inputs of the device, respectively. The fourth inputs of the memory blocks, the fifth inputs of the address blocks and the fifth output of the address signal generator are the second output One device, the sixth output of the address signal maker is connected to the sixth inputs of the address blocks. . 2. The device according to claim 1, that is, in that each address block contains AND elements from the first to the third, the first element. NOT, comparison blocks, first register, pulse generators, first switch and decoder, the output of which is connected to the first input of the second element AND, the second input of which is connected to the output of the first comparison unit, and the output connected to the input of the first element NOT and the first input of the first element AND , the output of the first pulse generator is connected to the first inputs of the first comparison and register unit, the second and third inputs of which are connected to the outputs of the second pulse generator and the First Electroscope, respectively, and the output terminal with the first input of the second comparison unit, whose input is connected to the first input of the third element AND, the second input of which is connected to the output of the first element NOT, and the output to the first input of the first switch, whose output is the output of Form 05, the input device of which is , OD, respectively, of the second high voltage switch and the nepjjoro input from the decoder, the second input of the first comparison unit, the fourth input of the first register, the second input of the second comparison unit and the third input of the first comparison unit, the third input comparing unit, the second input of the second AND gate 3. The apparatus of claim 1, m l of ichayuschee that the generator contains items of address signals and the fourth to the twelfth, NLP element, a second element

Description

NOT, RS flip-flop. From the first to the fourth, B-flip-flop, drivers from the first to the eighth signals, registers from the second to the fourth, first and second shift registers, a counter, switches from the second to the fourth, groups of amplifiers, third comparison block, the second decoder, the delay element and the third pulse generator, the output of which is connected to the first-inputs of elements AND from the fourth to the seventh and through the second element NOT to the C inputs of the D flip-flop, the first shift register and to the input of the delay element. С-outputs second and third registers are connected to With the outputs of the fourth and fifth elements And, the output of the sixth element And is connected to the first R-input of the first RS-flip-flop, the output of which is connected to the D-input of the D-flip-flop, the output of the seventh element And is connected to the C-inputs of the fourth register counter and with the S inputs of the first RS trigger and the second shift register, the C input of which is connected to the output of the eighth element And, the first output of the first shift register is connected to the first input of the second decoder, the output of which is connected to the first input of the third comparison unit, the second first output gistra shear is connected. with the first inputs of the seventh driver and the second switch, the output of which is connected to the D input of the fourth register, the third code of the first shift register is connected to the second input of the second switch, the fourth output of the first shift register is connected to the third input of the second switch and the first input of the ninth And element whose output is connected to the counting input of the counter, the fifth output of the first shift register is connected to the D input of the first shift register, to the second inputs of the fourth and fifth And elements, to the first and to the inputs of the eighth About and the tenth elements And, with the R-input of the second RS-flip-flop and with the twisted input of the second switch, the inputs from the fifth to the eighth of which are connected respectively to the outputs of the fourth register and the first to third signal conditioners, the first output of the second shift register is connected to the second input of the seventh is formed (al signals, the first output of which is connected to the ICs of the amplifiers of the second group, the second switch, to the S inputs of the second and third RS flip-flops, the second output of the second shift register is connected to the third inputs And the seventh signal generator, the second output of which is connected to the second inputs of amplifiers of the second group, the third switch, the first inputs of the fourth switch and the eleventh And element, the third output of the second shift register is connected to the D input of the second shift register, with the third input that element And with the fourth input of the seventh signal generator, the third output of which is connected to the third inputs of the amplifiers of the second group, the third switch, with the second inputs of the fourth switch, six And, with the R input of the fourth RS flip-flop and through the fifth signal conditioner — with the first input of the OR element, the output of the eleventh AND is connected with the R input of the third RS flip-flop and the S input of the fourth RS flip-flop, the output of which is connected with the second input of the tenth element And, the output of which is connected to the R input

the second shift register, the outputs of the second and third RS-flip-flops are connected respectively to the second inputs of the ninth and eighth elements And, the output of the second register is connected to the fourth input of the third

commutators (pa, the output of which is connected to the inputs of amplifiers of the third group, the first and second outputs of the third register are connected respectively to the second input of the eleventh element I and to the third input of the fourth switch, the output of which is connected to the first: inputs of amplifiers of the first group, first output -O- the trigger is connected to the second input of the seventh element And, the third input of which is connected to

the first input of the twelfth element And with the output of the third unit of comparison, BTOpoii output D-TpHr.repa is connected to the fifth input of the seventh signal conditioner and the second input of the Twelfth element And, the output of which through the sixth signal conditioner is connected to the second input

the house of the OR element, whose output is connected to the second inputs of amplifiers of the first group, the output of the fourth signal conditioner is connected to the second input of the third comparison unit and the fifth input of the third switch, the input of which is connected to the fourth input of the fourth switch and the counter output, the first outputs of the amplifiers of the third group are connected to the third input of the third comparison unit; the amplifiers of the third group are connected to the fourth input of the third comparison unit; the output of the eighth for96949

The signal generator is connected to the second R-input of the first RS-flip-flop, to the R-input of the D-flip-flop and to the S-input of the first shift register, the D-inputs of the second and third registers being the input of the block whose outputs are the output of the delay element ,, output of the second compressor, third input of the first shift register, outputs of amplifiers of the first group, fifth output of the first shift register, first and second outputs of amplifiers of the third group, outputs of amplifiers of the second group.

The invention relates to computing and can be used in the construction of multiprocessor computing systems.

The purpose of the invention is to increase the capacity of the device.

Figure 1 shows a structural diagram of a storage device; figure 2 - block diagram of the address block; figure 3 - structural diagram of the driver address signals.

The memory device (Fig. 1) contains memory blocks 1-6, address, blocks 7-12, and a driver. 13 address signals.

Each of the address blocks 1-6 contains (FIG. 2) elements I. 14 | -14z from the first to the third, input buses 15, the first element NOT 16, the first 17 and the second 18 comparison blocks, the first decoder 19, the first register 20, the first pulse generator 21, second pulse generator 22 and first switch 23.

Shaper 13 address signals (Fig. 3J contains the elements AND 24-32- from the third to the twelfth, the element OR 33, the second element is NOT 34 RS-flip-flops 35-38 from the first to the fourth, D-flip-flop 39, shapers 40-47 from the first eighth, second 48, third 49 and quarter 60 registers, first 51 and second 52 shift registers, counter 53, second 54, third 55 and quarter 56 switches, first 57, second 58 and third 59

groups of amplifiers, a third comparison unit 60, a second de-amplifier 61, a delay element 62 and a third pulse generator 63. .

The device is working as follows.

Several computers are connected to the device (not shown). Each computer accesses the storage device in strictly reserved for it.

time The address issued by the computer is supplemented by the shaper 13 by the address of the computer, which, together with the highest part of the address from the computer, enters all the address blocks 7-12. Here, they are compared with the stored address of memory blocks 1-6. The address block, which determined the paiseHCTBo-received composite address with the stored one, transmits the received command to the corresponding memory block, which executes it. Since shaper 13

for each computer it gives different addresses of the computer, then each computer has its own groups of memory blocks available and not

memories of other computers are available, the existence of which they may not know. This mode of operation of the computer, connected to this storage device, corresponds to the mode of operation of three independent one from the other computer. The exchange of information between computers is carried out. shaper 13 according to a program written for it by one of the computers and placed in one of the memory blocks. Elementary

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The address of this program. The computer records at the agreed address. This record is the signal for starting the former 13, it reads two words of the program. The first word indicates the source address of the memory block. The second word indicates the address to be assigned to this block of memory. Based on these words, the shaper 13 issues the command Write address, and the address block corresponding to the required memory block executes it and stores the new address for the memory block. So addresses can be replaced for any number of blocks of memory. After that, each computer has access to new groups of memory blocks.

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So, the shaper 13, interacting with the address blocks, provides for the installation of additional memory blocks, which allow 5 not only all three computers to have access to

the maximum possible for her memory. but also allocate the same amounts of memory to conditional computers. In addition, this interaction ensures the operative transfer of any number of memory blocks from one computer to the second, i.e. virtually every computer is given the opportunity to work with

operational memory, significantly exceeding the maximum capacity; addresses of access to the storage device.

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Claims (3)

1. A MEMORY DEVICE containing memory blocks, the first and second inputs and outputs of which are respectively the first and second inputs and the first output of the device, the address blocks whose outputs are connected to the third inputs of the corresponding memory blocks are typical. C. with the fact that, in order to increase the capacity of the device, an address signal shaper is introduced into it, the input of which is connected to the outputs of the memory blocks, the first and second outputs are connected to the first and second inputs of the memory blocks and address blocks, the third and fourth outputs of the shaper address signals and the third and fourth inputs of the address blocks are the third and fourth inputs of the device, respectively. The fourth inputs of the memory blocks, the fifth inputs of the address blocks and the fifth output of the address signal shaper are the second output of the device The sixth output of the address signal generator is connected to the sixth inputs of the address blocks. 2. The device according to claim 1, wherein each address block contains AND elements from the first to the third, the first element. NOT, comparison blocks, first register, pulse generators, first switch and decoder, the output of which is connected to the first input of the second element AND, the second input of which is connected to the output of the first comparison unit, and the output is connected to the input of the first element NOT and the first input of the first element ' And, the output of the first pulse generator is connected to the first inputs of the first unit of comparison and register, the second and third inputs of which are connected respectively to the outputs of the second pulse generator and the first element And, and the output is connected to the first input the house of the second comparison unit, the output of which is connected to the first input of the third AND element, the second input of which is connected to the output of the first element NOT, and the output - with the first input of the first switch, the output of which is the output of the shaper, the inputs of which are, respectively, the second input of the first switch and the input of the first decoder, the second input of the first comparison unit, the fourth input of the first register, the second input of the second comparison unit and the third input of the first comparison unit, the third input of the second comparison unit, the second input second element I. 3. The device according to claim 1, wherein the address signal generator comprises AND elements from the fourth to twelfth, an OR element, a second element CD □ 5 CD CD NOT, RS-triggers. From the first to the fourth, D-flip-flop, the drivers of the signals from the first to the eighth, the registers from the second to the fourth, the first and second shift registers, the counter, the switches from the second to the fourth, the amplifier groups, the third comparison unit, a second decoder, a delay element and a third pulse generator, the output of which is connected to the first inputs of the AND elements from the fourth to the seventh and through the second element NOT to the C-inputs of the D-trigger, the first shift register and the input of the delay element, C-outputs of the second and third registers are connected respectively specifically with the outputs of the fourth and fifth elements AND, the output of the sixth element And is connected to the first R-input of the first RS-trigger, the output of which is connected to the D-input of the D-trigger, the output of the seventh element And is connected to the C-inputs of the fourth register, counter and with S-inputs of the first RS-trigger and the second shift register, the C-input of which is connected to the output of the eighth element And, the first output of the first shift register is connected to the first input of the second decoder, the output of which is connected to the first input of the third comparison unit, the second output first register sd the yoke is connected to the first inputs of the seventh and the second generator switch, the output of which is connected to the D-input of the fourth register, third vkod first shift register connected to a second input of the second switch, fourth output of the first shift register is connected to a third input of the second switch and the first. the input of the ninth element And, the output of which is connected to the counting input of the counter, the fifth output of the first shift register is connected to the D-input of the first shift register, with the second inputs of the fourth and fifth elements of And, with the first inputs of the eighth and tenth elements of And, with the R-input of the second RS-flip-flop and with the fourth input of the second switch, the fifth through eighth inputs of which are connected respectively to the outputs of the fourth register and signal conditioners from the first to the third, the first output of the second shift register is connected to the second input of the seventh signal shaper, whose output is connected to the first inputs of the amplifiers of the second group, the second switch, with the S-inputs of the second and third RS-flip-flops, the second output of the second shift register is connected to the third inputs of the fourth element And and the seventh signal shaper, the second output which is connected to the second inputs of the amplifiers of the second group, the third switch, with the first inputs of the fourth switch and the eleventh element And, the third output of the second shift register is connected to the D-input of the second shift register, with the third input of the fifth element And and with the fourth input of the seventh signal conditioner, the third output of which is connected to the third inputs of the amplifiers of the second group, the third switch, with the second inputs of the fourth switch, the sixth element And, with the R-input of the fourth RS-trigger and through the fifth signal conditioner - with the first input of the OR element, the output of the eleventh element And is connected to the R-input of the third RS-trigger and the S-input of the fourth RS-trigger, the output of which is connected to the second input of the tenth AND, the output of which is connected to R-input the second shift register house, the outputs of the second and third RS flip-flops are connected respectively to the second inputs of the ninth and eighth elements AND, the output of the second register is connected to the fourth input of the third switch, the output of which is connected to the inputs of the amplifiers of the third group, the first and second outputs of the third register are connected respectively with the second input of the eleventh element AI with the third input of the fourth switch, the output of which is connected to the first. the amplifiers of the first group, the first output of the D-trigger is connected to the second input of the seventh element And the third input of which is connected to the first input of the twelfth element And and the output of the third comparison unit, the second output of the D-trigger is connected to the fifth input of the seventh signal conditioner and to the second the input of the twelfth AND element, the output of which through the sixth signal conditioner is connected to the second input of the OR element 1196949, the output of which is connected to the second inputs of the amplifiers, of the first group, the output of the fourth signal conditioner is connected inen with the second input of the third comparison unit and with the fifth input of the third switch, the Sixth input of which is connected to the fourth input of the fourth switch and with the output of the counter, the first outputs of the amplifiers of the third group are connected to the third input of the third comparison unit, the outputs of the amplifiers of the third group are connected to the fourth input of the third comparison unit, the output of the eighth signal conditioner is connected to the second R-input of the first RS-trigger, with the R-input of the D-trigger and the S-input of the first shift register, and the D-inputs of the second and third register the ditches are the input of the block whose outputs are the output of the delay element. the output of the second switch, the third output of the first shift register, the outputs of the amplifiers of the first group, the fifth output of the first shift register, the first and second outputs of the amplifiers of the third group, the outputs, amplifiers of the second group.