SU1190518A1 - Modulo three counting device with check - Google Patents

Abstract

ACCOUNT DEVICE THROUGH MODULE THREE WITH CONTROL, containing an input bus, the first modulo-three counter, the second modulo-three counter, two modulo-two adders and the first OR element, whose inputs are connected to the outputs of the first and second modulo-two adders, the first inputs of which connected respectively to the direct outputs of the first and second bits of the first modulo three counter, the counting input of which is connected to the counting input of the second counter modulo three and the input bus, characterized in that, in order to increase the depth of the counter l, four AND elements are entered into it, the second and third OR elements, and as the second counter modulo three a three-digit ring shift register is used, the direct outputs of the second and third bits of which are connected respectively to the second inputs of the first and second modulators two, the output of the first element OR is connected to the first input of the second element OR, the second input of which is connected to the output of the first element AND, the first and second inputs of which are connected respectively to the direct outputs of the first and second bits modulo three, the third input of the second element OR is connected to the output of the third element (OR, whose inputs are connected respectively to the outputs of the second, third and fourth elements AND, the inputs of the second element AND are connected to the direct outputs of the first, third and c the inverse output of the second bit of the ring shift register, the direct outputs of the first, second and inverse output of the third bit of which are connected to the inputs of the third element, And the inputs of the fourth element, And are connected to the inverse outputs rows ring shift register. 00

Description

The invention relates to automation and computing and can be used to control redundantly encoded synchronous digital devices. The aim of the invention is to increase the depth of control by monitoring failures leading to the transfer of two counting channels to the same, unused (prohibited) ones in the failure operation cycle.

FIG. 1 is a diagram of a calculating device modulo three with control; FIG. 2 is a block diagram of a counting device with a control with two redundant channels with a control; FIG. 3 is a diagram of the calculating device modulo ten with control.

The device (figure 1) contains a ring register 1 shift with bits, counter 2 modulo three with bits and, adders and modulo two, elements AND 4-7, elements OR 8-10, input bus 11 n output bus 12 .

The inputs of the element OR 8 are connected to the outputs of the adders and the first inputs of which are connected respectively to the direct outputs of bits 2: 1 and 2: 2 of counter 2, the counting input of which is connected to the counting input of the ring shift register 1 and the input bus 11, the direct outputs of the discharge and the register 1 is connected respectively to the second inputs of the adders, and the output of the element OR 8 is connected to the first input of the element OR 10, the second input of which is connected to the output of the element AND 4, the first and second inputs of which are connected respectively to the direct outputs of the bits and counter 2, the third input of the element OR 10 is connected to the output of the element OR 9, whose inputs are connected respectively to the outputs of the elements AND 5-7, the inputs of the element AND 5 are connected to the direct outputs of the bits and to the inverse output of the register 1, etc. My outputs of bits and of which the inverse code of bits of which is connected to the inputs of the element And 6, the inputs of the element And 7 are connected to the inverse outputs of the bits of the register 1, the output bus 12 is connected to the output of the element OR 10.

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The adders and and the OR element 8 constitute the code comparison node. Counter 2 operates in the code 00, 10, 01, 00, ..., and the ring register 1 in the code 100, 010, 001, 100, ....

Element AND 4 is a latch of an unused state of 1l counter 2. Elements AND 5-7

and the element OR 9 constitutes a latch of unused states 000, 110, 101 of the ring register 1. Instead of the elements OR 8-10, one element OR having seven

inputs.

The device works as follows.

In the initial state at the outputs of register 1 there is a code 100, and

at the outputs of the counter 2 - code 00 (the circuit of the installation in Fig. not shown). During normal operation of the device, when receiving counting pulses through the bus, 11 codes at the outputs of bits and

 register 1 and at the outputs of the bits and the counter 2 correspond to one another, therefore the output of the comparison node (the output of the element OR 8) is a zero signal and, accordingly,

output bus 12 is also a zero signal. If there is a failure in the set of allowed states, then the states of the corresponding bits of register 1 and counter 2 do not correspond to one

to another and, therefore, at the output of the element OR 8 and at the output of the element OR 10 - a single signal.

In case of failure in the set of forbidden (unused) states

the register 1 or counter 2 at the outputs of the corresponding latches of unused states (element output OR 9 or element output 4) is a signal of a logical unit and, in some cases, at the output element OR 8. also a signal of a logical unit, which leads to the appearance of an error signal on the output bus 12.

The device (Fig. 2) contains an input bus 13, counting channels 14 and 15, a comparison unit 16, latches 17 and 18 unused states, an OR element 19, an output bus 20 and an installation bus 21.

The input bus 13 is connected to the counting inputs of the counting channels 14 and 15, the outputs of which are connected respectively to the first and second groups of

3

Having supplied the comparison unit 16 and, respectively, with the inputs of the latches 17 and 18 unused states, the outputs of which are connected to the inputs of the element OR 19, the additional input and output of which are connected respectively to the output of the comparison block 16 and the output bus 20, the bus 21 is connected to the inputs of the initial installation of counting channels 14 and 15.

In the case of using counters with the same module but different sizes as counting channels, the comparison block contains a combination logic part (code converter) or ROM to bring the operation code of the first counter to the operation code of the second counter and the bit comparison code comparison that compares the mismatch code of the second counter and the converted code of the first counter.

Each latch of unused states is implemented on the AND-OR element, which implements the minimum disjunctive function of all prohibited states of the corresponding counter.

The device (figure 2) works similarly to the device (figure 1).

In case of using identical counters as counting channels, there is no need for

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application of one of the fixators of prohibited states.

The device (FIG. 3) contains an input bus 22, binary-decimal 5 counters 23 and 24 operating in a code, a comparison unit 25, element OR 26, element AND 27, element OR 28, output bus 29 and installation bus 30 .

10 Bus 22 is connected to counting inputs of counters 23 and 24, the outputs of which bits are connected respectively to the first and second groups of inputs of node 25, the output of which is connected to the first input of the element

OR 28, the second input of which is connected to the output of the element AND 27, the first and second inputs of which are connected respectively to the output of the last

20 bits of the counter 23 and the output of the OR element 26, the inputs of which are connected to the outputs of the second and third bits of the counter 23.

Elements 26 and 27 constitute the fictaTop unused 1) 1X state with codes of numbers from ten to fifteen.

Any simultaneous failure of counters 23 and 24 into the same forbidden state is not detected by node 25, but is detected by the lock of unused states.

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Claims (1)

COUNTER MODULE FOR THREE MODULE WITH CONTROL, containing the input bus, the first counter modulo three, the second counter modulo three, two adders modulo two and the first element OR, the inputs of which are connected to the outputs of the first and second adders modulo two, the first inputs of which connected respectively to the direct outputs of the first and second bits of the first counter modulo three, the counting input of which is connected to the counting input of the second counter modulo three and the input bus, characterized in that, in order to increase the depth of control, not o four AND elements are introduced, the second and third OR elements, and a three-digit ring shift register is used as the second counter modulo three, the direct outputs of the second and third digits of which are connected respectively to the second inputs of the first and second adders modulo two, the output of the first OR element connected to the first input of the second OR element, the second input of which is connected to the output of the first AND element, the first and second inputs of which are connected respectively to the direct outputs of the first and second bits of the first modulo three, the third input of the second OR element is connected to the output of the third OR element, the inputs of which are connected respectively to the outputs of the second, third and fourth AND elements, the inputs of the second AND element are connected to the direct outputs of the first, third and inverse outputs of the second bits of the ring register a shift, the direct outputs of the first, second, and inverse outputs of the third bits of which are connected to the inputs of the third element And, the inputs of the fourth element And are connected to the inverse outputs of the bits of the circular register . 1,190,518 A 1 1190518 2