SU1179430A1 - Device for servicing interrogations in domain memory - Google Patents

Description

The invention relates to computing and can be used when building storage devices on cylindrical magnetic domains (CMD) for 5

request queue service organizations by selecting a page write or read request,

the search time is minimal,

which allows to increase the actual 10

Some speed domain memory.

The aim of the invention is to increase the speed and reliability of the device.

FIG. 1 shows the functional scheme of the device for servicing requests in the domain memory; in fig. 2 - functional block of the priority block; in fig. 3 - functional diagram of the memory node; in fig. 4 - functional block diagram synchronization; figure 5 - the location of the pages in the storage drive on the CMD with block copying, 25.

including pages by addresses

2

which have read and write requests.

A device for querying in domain memory (FIG. 1) contains the first counter 1, the second counter 2, the first comparison node 3, the first memory block 4, the first register 5, the second register 6, the first multiplexer 7, the second multiplexer 8, the second block 9 memory, the third counter 10, the fourth counter 11, the second node 12 comparison, the third node 13 comparison, per-. 14, the second element is AND 15, the third element is AND 16, the fourth element is AND 17, the first element IS-NOT 18, the second element IS-NOT 19, the third multiplexer 20, the third register 21, the priority block 22 and the synchronization block 23. FIG. 1 shows the address inputs 24 and 25 of the device, the control input 26 of the device, the outputs 27 of the first register, the outputs 28 of the second register, the address outputs 29 of the device, the first input 30 and the second input 31

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priority block, the first output 32 and the second output 33 of the priority block, the single output 34 and the zero output 35 of the first comparison node, connected respectively to the third and fourth inputs of the priority block, the fifth input 36 and the sixth input 37 of the priority block, connected respectively to outputs of the senior categories 5ts and 6ts of the first and y

second registers, as well as with the first inputs of the elements And 16 and 17, the third output 38, the fourth output 39, the fifth output 40, the sixth outputs 41 and 42 and the seventh outputs 43 and 44 of the block, 5 priority, the input 45 controls the mode of circulation of memory blocks , the first outputs 46 and 47 of the synchronization unit, with the initial installation input to the zero-left state of the third register 21, the third inputs 48 of the first and third counters connected to the ninth input of the priority block and the third input of the synch block to output 47 - 25 ronization, the tenth entrance 49 and the eleventh input 50 of the block pr the priority, the second outputs 51 and 52 of the synchronization unit, the outputs 53 and 54 of the elements AND-NOT 18 and 19. ₃ 0

The priority block 22 (Fig. '2) contains the triggers 55-58, the elements AND 59-68, the elements AND-NOT 69-74, the elements OR' 75 -77, the element NOT 78, the node 79 of the reception. FIG. 2 shows a zero potential bus 80, a bus 81 with a logical unit potential of ³⁵ and the output of element 82 of the OR 75, as well as the δ-inputs of the initial installation to the single state, K, the inputs of the initial installation to the zero state synchronizing the C-inputs of the triggers 55 -58, 'informational вход-inputs of triggers 55-56, D-inputs and K — inputs of the triggers 57-58.

Receiving node 79 (FIG. '3) contains triggers 83-86, elements OR 87 and 88, elements AND 89-92, and AND-HE element 93. FIG. 3 shows 8 — the inputs of the initial installation to the single state, the E-inputs of the initial installation to the zero state, the synchronizing C-inputs of the flip-flops 83-86, the counting T-input of the flip-flop 83, the information D-inputs of the flip-flops 84-86.

The synchronization unit 23 (FIG. 4) contains registers 94-96, multiplexer 97, comparison node 98, elements OR 99 and 100, AND 101, triggers 102 and 103, and counter 104.

FIG. 4 shows the 8-inputs of the initial-installation in a single state E-inputs of the initial installation in the zero state, informational D-inputs, synchronizing the C-inputs of the triggers 102-103.

The device for servicing requests in the domain memory works as follows.

From the set of requests to read or write the page whose addresses are sent to address inputs 24 (read requests) and address inputs 25 (write requests) and are stored in memory block 4 (read requests) and memory block 9 (write requests ) in the form of a logical "1" in the ^ -th cell, the address of which coincides with the dm address of the page in the storage drive on the CMD (the absence of a request to the page ~ is encoded by the state of the logical "0" in the -th cell), one request per page is selected for servicing (reading or writing), time OISCA which in this cycle of the drive on the bubble is minimal. At the same time, the address of the readable or writable page is set at the address outputs 29, and at the output 41 of the reading or output 43 of the recording a resolving potential appears (logical "1") and from the beginning of the next clock cycle the reading is performed during the D cycles or the write during the C bars of the page . In the absence of permitting potentials at the outputs 41 or 43, there is no reference to the drive on the CMD. If there are permitting potentials at both outputs 41 and 43, the device is prepared for operation, there is no access to the drive, and at the input 48 there is a permitting potential, which takes the device to the initial state.

For reading the output closest to the register (replicators) or writing the page closest to the input / output register (exchange keys), taking into account the number of measures § for generating and placing the page in the corresponding positions of the input register5

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output (Fig. 5) using counter 2, the contents of which is one greater than the current page address located at the output register, and counter 11, the contents of which is (§ + 1) greater than the current page address located at the I / O register, addressing blocks 4 and 9 of memory, respectively, in the read mode of them, checks for the presence or absence of requests for the addresses of pages with minimal search time. The contents of counters 2 and 11 change synchronously. With the advancement of the CMD in the information registers of the accumulator, as the control input 26 of the device receives clock pulses with the frequency of the rotating field. Before starting work, the number 00 ... 01 is entered into counter 2, and the number 11 is entered into counter 11 (K + § + 1), where K is the number of ticks to advance the CMD from the input-output register to the output register, defining the position shift relative to the output register in the information registers in which the page is entered. If there are no requests for pages with addresses (ί-1) (for reading), and (ΐ- 1 + Κ + ς)

(on the record) during a tact, a check is carried out for the presence of requests to the pages ΐ and (+ Κ + §). If there is a request, the next clock cycle is either read the page or write (ί + Κ + §) -ή page. With simultaneous detection of read and write requests (Fig. 5, pages and (ί + Κ + §)), the lengths of the read request queues (the contents of counter 1) and the write (the contents of counter 10) are compared, the result of the comparison goes to the inputs 34 and 35 priority blocks. If the contents of counter 1 are less than or equal to the contents of counter 10, then the logical output “0” is present at the unit 34 output of the comparison node 3, the logical 1 is at zero 35, and the page write request is selected (recording priority).

Otherwise (the length of the queue of requests for reading is greater than the length of the queue of requests for writing) at the single output 34 of the node 3 the comparison potential is logical ”1",

zero - logical "0", selects the request to read the page (priority reading). Counters 1 and 10 are reversible: when you select a service request, their content is reduced by one, and when you add a request to the corresponding memory block, it increases by one. When a request is selected, its address (the contents of counter 2 or counter 11) is stored in register 21 and is present at address outputs 29 until the end of the request service.

In reading mode from blocks 4 and. 9 of the memory at the input 45 of the control of the conversion mode is set to the resolving potential, the addressing of the blocks 4 and 9 of the memory is carried out according to the contents of the counters 2 and 11, respectively. In the recording mode (at the input 45, logical "0") in blocks 4 and 9 of memory, they are addressed according to the contents of registers 5 and .6, respectively. When ha bit positions in the information registers of the drive on the CMD requests in blocks 4 and 9 of the memory are ordered in accordance with the physical addresses from. 0 to (t-1) pages of the drive. An additional (t + 1) -th cell in blocks 4 and 9 is entered, in which requests are not entered. Capacities of blocks 4 and 9 of memory are equal (t + 1) bits. A series of pulses arrives at the input 45 for controlling the treatment of memory blocks such that when each clock pulse arrives at the device control input 26, the reading mode begins and during the clock pulse arrival period an integer number of read-write inversion cycles are performed to memory blocks 4 and 9 and each The clock period ends with a write mode in blocks 4 and 9 of memory.

When preparing a device for operation, logical “0” values are entered into the cells of blocks 4 and 9 of memory with addresses 0– (t − 1). Addressing is carried out on the contents of the counters 2 and 11, at the output 40 of the priority block 22, the resolving potential. For this purpose, the input potential is fed to the input 48. Counters 1 and 10 are transferred to the zero state. Counter 104, triggers 102 and 103

7

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block 23 synchronization are transferred to the zero state, the output 47 logical "1". The triggers 55 and 56 of the priority block 22 are reset, the triggers 57 and 58 are transferred to one state, at the outputs 41 and 43 logical "1". The trigger 83 of the receiving node 79 is transferred to one state, at the output 40 of the priority block 22 a logical "1",

The registers 94-96 of the synchronization block 23 are entered into the numbers P, ϋ, C. At the outputs 32 and 33 of the block 22, the priority state of the logical "0". pulses at the control input 26 and the installation of the logical "O" at the input 45 of the control mode of treatment in blocks 4 and 9 of the memory on the numeric inputs are entered "About”. At the end of the recording "0" at the inlet 45 is established permitting potential. The address inputs 24 and 25 in bits 1- (p-1) of registers 5 and 6 are entered in the number w, and in the high-order digits 5ts and 6 _P - logical "O", so that before receiving the first requests the logical "1" is recorded in additional cells with the address m of blocks 4 and 9 of memory, and the reading at this address is not performed. The resolving potential at inputs 45 and 48 is removed. To the control input 26, clock pulses are fed to the input of the counter 104 of the synchronization unit 23 (FIG. 4). The number of P switches to the inputs of the multiplexer 97 in accordance with the table. 1. When the contents of the counter 104 become equal to P, the triggers 55-58 of the priority block 22 · (FIG. 2), 84 of the receiving unit 79 (FIG. 3), 102 and 103 of the synchronization unit 23 are reset. The counter 104 is also transferred to the zero state. The number 00 ... 01 is entered into counter 2, the number is entered into counter 11 (K + § + 1). The device is ready for operation.

I

In the absence of reading or writing the page with the arrival of each clock pulse to the control input 26 of the device, the presence of requests by addresses in the counters 2 and 11 begins by checking the information from memory blocks 4 and 9 in the first circulation cycle and (or) the fact incoming requests to current addresses. Addresses of requests are taken to bits 1— (n — 1) of registers 5 and 6 when there is a logical “1” at the input 45 for controlling the treatment of memory blocks and at outputs 38 and 39 for block 22 of the priority potential, and to bits 5a. and b ^ always enter "1", which translates the triggers 85 and 86 of the receiving unit 79 (FIG. 3) into a single state.

In this case, the reception of new requests is blocked until the end of the recording of the incoming request to memory blocks 4 and 9, since the resolving potentials at the outputs 38 and 39 of priority block 22 are removed. Signals from the outputs of bits 5 ₍₁ and 6 ^, passing through AND elements 16 and 17, increase the contents of the counters 1 and 10. If the request address matches the current address (the state is logical "1". At the outputs of the comparison nodes 12 and 13), there is no service request (logical "1" at the output 51 of the synchronization unit 23) but the selection of the request has already taken place ("1" at output 41 or 43 of block 22, with rhythm), then the contents of counters 1 and 10 do not increase. When a logical 'Ί "appears on one of the outputs 41 and 43, the contents of the corresponding counter 1 or 10 decrease by one. In the absence of the request service and the corresponding address received in registers 5 and 6 with the corresponding current address in counters 2 and 11, the request is not entered into blocks 4 and 9 of memory, and with the start of reading or writing (at the output 51 of synchronization unit 23 a logical “0” appears), its address is switched by multiplexer 20 in accordance with maintenance mode and stored in register 21 until the end of reading or writing (the appearance at the outputs 46 and 47 of the synchronization block 23 logical "1"), if there are no logical "0" at the outputs 42 and 44 of the block 22 priority.

Depending on the type of read,

from blocks 4 and 9 of memory in the first cycle of circulation information is possible

one of the following operating modes

in the absence of new requests, ad1179430

reza which coincide with the current.

1. No requests for current addresses. ' The output 40 of block 22 priority level of logical "0", $

When writing, blocks 4 and 9 of memory are written using registers 5 and 6, and at the 32 and 33 numerical inputs there are logical "1" entered at addresses that do not coincide with the current ones.

2. Reading the page write request. The trigger 56 of the block 22 priority (Fig. 2) is translated into one state, at the output of the element And 63 logical "0". Thereby, data reception from the numerical outputs 30 and 31 of blocks 4 and 9 of memory is blocked in subsequent access cycles until the end of the page writing to the drive on the CMD. When the "0" appears at the input 45 of the control mode of treatment at the output of the record 43 is set resolving potential. The contents of the counter 10 is reduced by one. To the addresses in counters 2 and 11 when recording

in blocks 4 and 9 of the memory are recorded "0".

In the next cycle of accessing blocks 4 and 9 of memory, the reception of new requests is blocked (logical "0". On outputs 38 and 39) in case the first address cycle (in read mode) to registers 5 and 6 was <accepted request addresses, but due to the busy recording mode, when detecting a read request at the current address, requests were not recorded in blocks 4 and 9 of memory. The trigger 102 remains in the zero state until the next clock cycle. This will delay the start of recording until the page takes a corresponding position in the information registers of the drive on the CMD.

3. Reading a page read request. The trigger 55 is translated into a single state. Switching in priority block 22 occurs similarly to the previous mode. 50 At output 41 of the readout is set to allow the potential. Counter 1 is decreasing

per unit. In blocks 4 and 9 of memory at the addresses stored in the counters 2 55

and 11, are entered "0". From the next bar begins reading the page.

When writing or reading a page, as soon as the contents of the counter 104 become equal to the number C or 1) respectively, the triggers 55-58 of the priority block 22 (FIG. 2), 84 of the receive node and 79 of the receive (Fig. 3), 102 and 103 of the synchronization block 23 are reset. (Fig. 4), register 21 (Fig. 1). The counter 104 is also reset. The request service is over.

4. Reading requests to write and read various pages. The triggers 55 and 56 of the priority block 22 (FIG. 2) are transferred to a single state. Depending on the queue lengths of the write and read requests, when the "0" appears at the input 45, the state of the flip-flops 57 and 58 (Table 2) is determined and, accordingly, the read or write mode. When a read request is selected, “0” is entered in memory block 4 at the corresponding address, and “1” in memory block 9. When you select a write request in the memory block 4 is recorded "1", in the memory block 9 "0". The entry of information into the triggers 57 and 58 is performed in the write mode in the memory blocks 4 and 9, since in the read mode they can be. new requests will appear and the priority (state of outputs 34 and 35 of comparison node 3) may change. The signal "0" from the output 52 of the synchronization unit 23 allows to block the influence of the priority condition on the states of the outputs of the AND-NE 73 and 74 elements after selecting the service request. .

Requests whose addresses do not coincide with the current ones are entered into the corresponding memory blocks.

If the selection of the request has taken place, then the passage of the logical "1" signal from the output of the comparison node 12 is blocked when selecting a write request and the arrival of a read request at the current address or from the output of the comparison node 13 when selecting a read request and receiving a write request at the current address . Incoming requests are recorded in blocks 4 and 9 of memory.

If the request for the current address

arrives in the first circulation cycle

to blocks 4 and 9 of memory, then incrementing the contents of the corresponding counter 1 or 10 does not block 11,179,430

12

sya (at outputs 53 and 54 of the elements IS-NOT 18 and 19 logical 1 "), since the fact of the arrival of the request may be necessary when analyzing the priority condition.

Thus, the use of the invention will improve the speed of the device. The maximum value of the delay in queuing a request (enrolling it in memory blocks 4 and 9) does not exceed twice the value of the cycle time for accessing memory blocks 4 and 9, taking into account the time it was written, when a request was detected at the previous cycle for the current address. The actual performance of the domain memory when using the invention increases due to the lack of pre-queuing the request, if its address is the same as the current one, and

5 also by checking the presence of the request at the current address during the entire cycle of operation of the drive on the CMD, with the exception of the last recording mode in blocks 4 and 9 of memory. The reliability of the device is enhanced by blocking the reception of addresses of new requests until the end of the recording of a previously received request to the corresponding memory block. Besides.

5, the use of the invention allows to reduce the total capacity of memory blocks for storing requests to a value of 2 (w + 1) bits.

Table 1

Device operation mode Condition codes readout (41) records (43) multiplexer (97) Preparing the device for operation one one P number Read page one 0 Number ϋ Page record 0 one C number No requests for current addresses 0 0 Any numbers except 00 ... 00

The state of the inputs and outputs of the device in the first cycle of accessing blocks 4 and 9 of memory

table 2

Reading Record 40 thirty 31 Triggers Outputs AND NOT Outputs and A priority 32 33 BUT 41 43 40 73 I ⁷⁴ 65 66 34 I ³⁵ one 0 0 0 0 one one . 0 0 - one one 0 0 0 one 0 one 0 one one one 0 one - - 0 0 0 one one one one 0 one 0 one one one 0 - - 0 0 one 0 one one one one one one one 0 one 0 one 0 0 one one 0 one one one one one one 0 one 0 one 0 one one 0 0 one one

1179430

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FIG. 2

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fig.Z

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1179430

Register OUTPUT

L replicators

Write request

Read request

Keys exchange and

. Generator

Readout sensor

Annihilator

G7 Ha d X X d but X x $ at one one one --and ⁴ U * to X . X 7 1 t -G , Y

(ί + κ + d)

(from + to + d-1)

(ί ± κ)

(s-7 + k}

Register Vooooa — OUVODA

Annihilator

FIG. five

Claims (1)

A DEVICE FOR SERVICING INQUIRIES IN DOMATIC MEMORY, containing two counters, a comparison node, a memory unit, the outputs of the first counter are connected to the inputs of the first group of the comparison node, the first input of the second counter is the control input of the device, characterized in that, in order to increase speed and reliability devices, it contains three registers, three multiplexers _? the second memory block, the third and fourth counters, the second and third comparison nodes, the four AND elements, the two NAND elements, the priority block and the synchronization block, the inputs of the first groups of the first and second registers are device address inputs, the first input of the fourth counter is connected to the first input of the second counter, the outputs of the second and fourth counters are connected to the inputs of the first groups of the first and second multiplexers, to the inputs of the first groups of the second and third comparison nodes and to the inputs of the first group of the third multiplexer, output We are connected to the inputs of the third register, the outputs of which are the address outputs of the device,: the inputs of the second groups of the second and third comparison nodes are connected to the corresponding 'outputs of the first and second registers to which the inputs of the second groups of the first and second multiplexers are connected, the outputs of which are connected to the address the inputs of the first and second memory blocks, the outputs of the second and third comparison nodes are connected to the first inputs of the first and second And elements, the numerical outputs of the first and second memory blocks are connected The first and second inputs of the priority block, the first and second outputs of which are connected to the numerical inputs of the first and second memory blocks, respectively, the third and fourth inputs of the priority block are connected respectively to the single and zero outputs of the first comparison node, the inputs of the second group of which are connected to the outputs of the third the counter, the fifth and sixth inputs of the priority block are connected to the outputs of the senior bits of the first and second registers and the first inputs of the third and fourth elements And, the second inputs of which are connected to the outputs of the first and second elements, AND-NOT, the outputs of the third and fourth elements And connected to the summing inputs of the first and third counters, the third and fourth outputs of the priority block „ _I 3i,„ 1179430 1179430 connected to the inputs of the second groups of the first and second registers and to the inputs of the initial installation in the zero state senior bits of the first and second registers, the fifth output of the priority block is connected to the corresponding inputs of the first and second multiplexers, the sixth and seventh outputs of the priority block are the read and write outputs respectively and connected to the first and second inputs of the synchronization unit, to the subtractive inputs of the first and third counters, to the corresponding inputs of the third multiplexer, as well as to the second m inputs of the first and second elements Ii to the first inputs of the first and second elements AND-NOT, the second inputs of which are connected to the outputs of the first and second elements And the seventh input of the priority block is connected to the corresponding inputs of the first and second memory blocks and connected to the mode control input memory blocks, the eighth inputs of the priority block are connected to the first outputs of the synchronization block, one of which is connected to the initial setup input in the third state of the third register, the ninth input of the priority block is connected with the third inputs of the first and third counters, as well as with the third input of the synchronization unit, the tenth and eleventh inputs of the priority block are connected to the outputs of the first and second 'th elements AND', whose third inputs are connected to the corresponding input of the third multiplexer and connected to one of the second outputs the synchronization unit, the fourth input of which is the control input of the device, the fifth input of the synchronization unit is connected to the control input of the memory block handling mode, the twelfth input of the priority block is connected ugim of the second output synchronization unit. one