SU1140172A1 - Logic storage - Google Patents

Abstract

LOGICAL STORAGE DEVICE containing a pulse generator, an OR element, a trigger, an address register, an address counter, first, second and third accumulators, a comparison unit, the first AND element, a coincidence number counter and a threshold element, the first trigger input connected to the first input of the OR element The output of which is connected to the input of the address counter, the outputs of which are connected to the inputs for setting the address of the first storage device whose information input is the first information input of the device, the inputs for setting the address of the second The storage unit is connected to the installation inputs of the third storage unit, the output of the comparison unit is connected to the first input of the first element AND, the output of which is connected to the input of the counter of the number of matches, the outputs of which are connected to one of the inputs of the threshold element, the output of which is device output, characterized in that , in order to increase the reliability of the device, the signal distributor, signal conditioners, pulse generator, the second and third elements AND, the elements NOT, the input block of the starting address, with an adder, a multiplexer, a fourth accumulator, majority elements, a counter of the coincidence threshold number, the output of the pulse generator is connected to the first input of the first signal conditioner and to the input of the signal distributor, the first output of which is connected to the first inputs of the second and third signal conditioners and the pulse generator and the input the first element is NOT, the second input of the second signal conditioner is the synchronization input of the device, the first output is connected (L to the first input of the trigger, and the second oh output - to the second input of the third signal conditioner, the output of which is connected to the second inputs of the first trigger and the pulse generator, the first output of which is connected to the third inputs of the second and third signal conditioners, and the second output - to the second input of the element OR, the output of the trigger is connected to the first input of the second element I, the second input of which is connected to the output of the first element NOT, and the output to the control input of the first accumulator, the third input of the pulse shaper unit is connected to the first input su Matora, the second input of which is connected to the output of the address register, whose data input is connected to the data output block start address input, control output of which is coupled to a second input of the first signal shaper whose output is connected to the first controlled w

Description

The inputs of the address register and the input address input block, whose information inputs and information inputs of the second, third and fourth accumulators are the second information input of the device, and the address input is connected to the output of the second element NOT, the first input of the multiplexer is the address input of the device, the second IDC connected to the output of the adder, and the output to the inputs of the address setting of the second, third and fourth drives, the control inputs of which more often, the control input of the multiplexer and the input of the second element is NOT The control input of the device, the outputs on how to

The terminals are connected to the inputs of the respective majority elements, the outputs of the first and second majority elements are connected respectively to the first and second inputs of the comparison unit, the output of the third major element is connected to the second input of the first element I, the third input of which is connected to the second output of the third distributor and the first input of the third And, the second input of which is connected to the output of the fourth major element, and the output to the input of the counter of the coincidence threshold number, whose outputs are Eny with another input of the threshold element.

one

The invention relates to computing, in particular, to storage devices, and may be used to analyze binary code combinations.

A logical memory device is known that contains an input signal shift register, the direct output of each bit of which is connected to the first input of one of the elements AND whose outputs are connected to the corresponding readout buses of the magnetic core memory in which the standards are permanently sewn combined with each other, read pulses are applied to them, and the outputs of the memory device are connected to the threshold devices tl.

A disadvantage of this device is that it does not provide for the possibility of changing standards in the course of work, which limits its functionality.

The closest to the proposed is a logical storage device, consisting of: a pulse generator, a trigger, an NWH address register, an address counter, three accumulators, a comparison circuit, an AND element, a coincidence counter and a threshold element, and the first inputs of the trigger and the OR element interconnected output element OR

connected to the input of the address counter, the outputs of which are connected to the address setting inputs of the first storage device, whose information input is the device input, the address setting inputs of the second and third storage devices are connected to each other, the output of the comparison circuit is connected to the first input of the And element, the outputs of the coincidence counter are connected to the first inputs of the threshold element, the output of which is the output of the device. The principle of operation of this logical storage device is that the information in the sequential code is entered into it, then its contents are compared with the contents of the storage device, in which the reference sequence is stored, on the result of the comparison the mask is applied, the input pulse sequence is compared with the reference pulse, the number of matches of the incoming pulse and the reference pulse is counted by the counter and fed to the input then The final element, where it is compared with the number of coincidences Bbw, the result of the comparison is fed to the output of device 2.

The disadvantages of this device are its limited functionality, since it does not provide for joining the device with a micro-computer for a more rapid change of the reference combination during operation, as well as the possibility of promptly changing the threshold number of matches, and the reliability of the device is low due to the lack of duplication of the binary combination. the reference combination and masks. The purpose of the invention is to increase the reliability of the device. The goal is achieved (in that the logical memory containing the pulse generator, the OR element, the trigger, the address register, the address counter, the first, second and third accumulators, the comparison unit, the first AND element, the counter of the number of coincidences and the threshold element, the first the trigger input is connected to the first input of the OR element, the output of which is connected to the input of the address counter, the outputs of which are connected to the inputs of the address setting of the first storage device, whose information input is the first information input the device, the inputs for setting the address of the second accumulator are connected to the inputs of the installation of the third accumulator, the output of the comparison unit is connected to the first input of the first element I, the output of which is connected to the input of the counter of the number of coincidences whose outputs are connected to one of the inputs of the threshold element, output which is the output of the device, the signal distributor, signal conditioners, pulse generator, second AND third AND elements, NOT elements, initial address input block, adder, multiplexer, quad are entered. the accumulator, the majority elements, the counter of the coincidence threshold number, the pulse generator output being connected to the first input of the first signal conditioner and to the input of the signal distributor, the first output of which is connected to the first inputs of the second and third signal conditioner and the pulse generator and the input of the first element is NOT, the second input of the second signal conditioner is the synchronizing input of the device, the first output is connected to the first input of three heres, and the second output is connected to the second inlet 724 of the third About the signal conditioner, the output of which is connected to the second inputs of the first trigger and the pulse generator, the first output of which is connected to the third inputs of the second and third signal conditioners, and the second input to the second input of the IZH element, the output of the trigger is connected to the first input of the second element And , the second input of which is connected to the output of the first element NOT, and the output to the control input of the first accumulator, the third output of the pulse generator is connected to the first input of the adder, the second input of which is connected to output of the address register, the information input of which is connected to the information output of the input address input unit, the control output of which is connected to the second input of the first signal conditioner, the output of which is connected to the control inputs of the address register and the input address input block, whose information inputs and information the inputs of the second, third and fourth drives are the second information input of the device, and the address input is connected to the output of the second element NOT, the first input of the multiplexer in The address input of the device, the second input is connected to the output of the adder, and the output is connected to the address setting inputs of the second, third and fourth drives, the control inputs of which, the control input of the multiplexer and the input of the second element are NOT the control input of the device, the outputs of the drives are connected the inputs of the corresponding schema of the majority elements, the outputs of the first and second majority elements are connected respectively to the first and second inputs of the comparison unit, the output of the third majority element is connected to the second at the input of the first element And, the third input of which is connected to the second output of the signal distributor and to the first input of the third element And, the second input of which is connected to the output of the fourth major element, and the output to the counter input of the threshold number of matches, the outputs of which are connected to another input of the threshold an item. FIG. 1 shows a block diagram of the proposed device;

in fig. 2 - functional diagram of the signal conditioner; in fig. 3 structural diagram of the pulse builder.

Logical memory device contains (Fig. 1) pulse generator 1, signal distributor 2, first 3, second 4 and third 5 signal conditioners, first 6 and second 7 elements NOT, driver 8 packs of pulses having inputs 9 and 10 and outputs 11- 13, the first trigger 14, the element OR 15, the address counter 16, the first 17, the second 18 and the third 19 elements AND, the initial address input block 20 having inputs 21 and 22 and outputs 23 and 24, input 25 of address register 26, adder 27 , multiplexer 28, first 29, second 30, third 31, and fourth 32 drives, respectively having information These inputs 33-36, inputs 37-40 for setting the address and control inputs 41-44, first 45 second 46, third 47 and quarter 48 major elements, comparison block 49, match number counter 50, threshold number counter 51 and the threshold element 52.

The shaper 4 signals (figure 2) contains the second 53 and third 54 triggers and the element AND NOT 55 and works as follows.

At the first input of the element IS-HE 55, which is connected to the synchronization inputs of the flip-flops 53 and 54 and which is the first input of the shaper, the synchronizing pulses are applied. The trigger data input 53, which is the driver input, receives a triggering pulse with duration t at that 1: 1,) fj, where IX; sync pulse duration. In this case, the output of the trigger 53, which is connected to the second input of the AND-HE element 55 and the data input of the trigger 54, at the time of arrival of the first sync pulse in the time period 1, appears the potential potential. At the inverse of the output of the trigger 54, connected to the third input of the element IS-HE 55, a potential of zero appears at the moment of arrival of the second in the period of time f. sync pulse. Thus, at the output of the element AND-HAN 55, which is the first output of the driver, a zero pulse is formed in the driver; the tj value, corresponding in time to the first sync pulse in the time period t.

At the direct output of the trigger 54, which is the second output of the driver, a single potential is set at the moment of arrival of the second one in the time period. T sync pulse. The flip-flops 53 and 54 are reset to the state O with the arrival on the third. the input of the driver, connected to the inputs of the installation in the O flip-flops 53 and 54, pulse reset.

The composition and operation of the formers 3 and 5 of the signals are similar to the composition and operation of the imager 4.

The shaper 8 bursts of pulses (Fig. 3) consists of the fourth 56 and fifth 57 flip-flops, the third 58 and the fourth 59 NO elements, the fourth element I 60, the fourth 61 and the fifth 62 signal shapers and the counter 63.

. Shaper 8 packs of pulses is as follows.

At input 9, clock pulses are received, at input 10, a trigger pulse that switches trigger 56 to state 1. A single potential from the output of trigger 56 enters input of element I 60 and opens it to pass clock pulses that pass from output of this element to output 12 the driver and the cell element HE 58 to the input of counter 63, which is configured to count N pulses (N is the length of the reference combination). With the arrival of the N-ro clock at the output of the counter 63, an overflow signal appears, switching the trigger 57 to state 1. A single potential from the output of the trigger 57 triggers the driver 61, at the first output of which a pulse appears that triggers 56 57 and through the element 59 the counter 63 and at the second output - a single potential, starts the driver 62, the output of which with the arrival of the next clock pulse is the pulse arriving at the output 11 of the driver 8 packs of pulses. Thus, a bundle of N pulses passes at output 12 of driver 8, a pulse is signaled at output 11, signaling the end of the passage of a packet of N pulses, at exit 13 codes of numbers sequentially varying from 1 to N

Shapers 61 and 62 are similar in composition and principle of operation to shaper 4.

71

The initial address input unit 20 can be implemented on the LSI K580IK55. Its input 22 is intended for selecting an LSI chip, output 24 and input 25 for exchanging signals with the driver 3.

Drives 29, 30, 31, and 32 are made on semiconductor memory circuits, each drive having three independent memory areas (e.g., 29, 29, and 29 for drive 29), whose respective inputs are interconnected. The control inputs 41-44, respectively, of the accumulators 29-32 are designed to control the write-read modes.

The operation of the device is as follows.

The device allows analyzing binary code combinations of arbitrary length, not exceeding the volume of the first accumulator 29, and operates in the Record Reference and Analysis modes.

Record reference mode.

A potential is set at the control input of the device, switching the accumulators 30-32 to Record mode and opening one of the multiplexer 28 inputs. At the address inputs of the device, a number in the binary code is not greater than M, such that LM N, where L is some, for example the maximum possible number that can be found in the address counter 16. In the second accumulator 30, the first bit of the reference pattern is entered, S the third accumulator 31 is the first bit of the mask, which is a binary combination of a code containing, like the reference combination, N bits and characterized by the fact that a certain bit in it takes the value 1, if the corresponding bit of the reference combination is taken into account when analyzing the received combination, or O otherwise, at the same time, the fourth bit 32 is entered into the fourth drive, the first bit is such a binary combination, that the sum of the bits, taking the value 1, corresponds to There is a threshold number of matches for the received and reference combinations, which takes into account when analyzing the received combination. Each drive is recorded in three independent

eight

the memory areas, respectively, indicated for the second accumulator DZ, 30 and 30, for the third accumulator 31, 31, and for the fourth accumulator 32, 32 and 32. Then the number set at the address inputs of the device is sequentially increased by one synchronously with the change {on the information inputs of the bits of the reference combination, mask and combination of the threshold number of matches until the second 30, third 31 and fourth 32 accumulators are listed N bits of the corresponding binary combinations, and in each drive, these combinations occupy sequentially N cells. Then, a potential corresponding to the read mode is set at the control input of the device. This potential switches the second 30, third 31 and fourth 32 drives to the Read mode, opens the other inputs of the multiplexer 28 and, inverted by the NOT element 7, is fed to the input 22 of the input unit 20, preparing it for data reception. After that, the device can work in the Analysis mode.

Analysis mode.

The clock pulses accompanying the binary-coded information and the correspondence in time to the beginning of each bit are sent to the synchronizing input of the device. The input of the distributor 2 receives pulses from the generator 1, the next with a frequency F, the value of which satisfies the condition where the frequency of the clock pulses. Synchronizing pulses with a duration of 1/6 F with a frequency F from the first output of the distributor 2 are fed to the inputs of the formers 4 and 5 and the former of the 8 packs of pulses. The clock pulse arriving at the synchronization input of the device starts the driver 4, which forms at its first output. a single pulse with a duration of 1/6 corresponding to the time of the beginning of a clock pulse with a duration of 1 / f. The pulse from the first output of the imaging unit 4 switches the trigger 14 to the state 1 and passes through the element OR 1 to the input of the counter 16 of the address. The potential from the second output of the former 4 starts the formation9

The pulley 5, at the output of which a pulse with a duration of 1/6 F is formed, is shifted in time by 1 / F relative to the pulse at the output of the shape of the body 4. This pulse switches the trigger 14 to the state O and starts the shaper 8 forming the output 11 the reset pulse to the initial state of the formers 4 and 5, and at the output 12 - a pack of N pulses passing through the OR 15 element to the input of the counter 16. From the output of the trigger 14 to the input of the And 18 element, a 1 / F pulse corresponding to time with its leading edge to the beginning of the clock pulse, at the same time, another element of element 18 is inverted by the element NOT 6 pulses from the first output of the distributor 2. The element 1.8 forms at its output a recording pulse arriving at the input 41 of the first accumulator 29 and switching the last into the Record mode. the information input of the device is recorded by drive 29 into a memory cell with an address set at the outputs of counter 16. After finishing writing to the first drive 29, the potential at its input 41 changes and switches the drive 29 into Read mode. At the device input, an initial address code is set, which determines the number of the cell from which the reading of the accumulators 30, 31 and 32 begins, and is received at the inputs 21 by the block 20 under the action of the control signal at its input 22 After receiving the information on the output 24 of the block 20 a signal appears that triggers shaper 3, the first input of which receives synchronized pulses from the output of generator 1, shaper 3 generates at its output a pulse arriving at input 25 of block 20, preparing the latter for receiving new information, and at the input a register 26, which, under the action of a control signal, rewrites the code of the starting address from the outputs 23 of block 20, the code of the starting address from the outputs of register 26 is entered on one input of the adder 27, on the other inputs of which enter numbers of numbers sequentially varying from 1 to N, from the outputs of the 13 shaper 8.

140172

ten

 The adder 27 summarizes the code of the starting address with successively varying codes of numbers from 1 to N, the result of summing through multiplexer 28 is fed to the inputs 38-40 of setting the address, respectively, of the accumulators 30-32. Information from the outputs of the three memory areas of each accumulator 29-32 goes to three inputs, respectively, of the majority elements 45-48, which, at their outputs, form codes corresponding to Equal codes on any at least two of their inputs.

5 in the time interval between two adjacent clock pulses from the second 30, third 31 and fourth 32 drives all N bits of the reference combination, masks are read

0 and combinations of the threshold number of matches, respectively. At the same time f, one bit is written to the first drive 29 on its binary information-input information input 33 and a combination of N previously recorded bits is read, including the bit recorded in the same time interval t. In this case, the bit recorded last

0 time is read last in combination, i.e. if the last write is made to the cell of the first accumulator 29, the reading begins (d + 1) -th cell and ends with the j-th cell, which is ensured by automatic reset of the counter 16 after the next burst of pulses arrives at its input. Since in time intervals

the first accumulator 29 is accessed N + 1 times (1 time - write, N times - read), and the second 30, third 31 and fourth 32 drives - only N times (read),

5 to every following interval

the time of bitwise comparison of the received and reference bit combinations in the i-th cell of the first accumulator 29 is sequentially compared with the bit stored in the i-th, (1-1) -th, (1-2) -th, ( 1-3),, .., Lth, a-1) -th, ..., (1 + 2) -th „(i + 1) -th cell of the second drive 30, then in ( The 1 + 1) cell of the first accumulator 29 records another bit of the received binary-coded information, i.e. the comparison is carried out in such a way that the received combination in each subsequent interval Γ, when compared with the reference combination, is shifted by one bit relative to the last one.

The compared bats of the received and reference combinations are exposed at the outputs of the first 45 and second 46 major elements, respectively. When the compared bits match, the comparison unit 49 generates a pulse arriving at the input of element AND 17, to another input of which the corresponding mask bit is output from the output of the third major element 47, and to the third input - strobe pulses with a duration of 1/3 F from the second output of the distributor 2, shifted in time by 1/3 F relative to the pulses at the first output of the latter. The same strobe pulses are applied to the input element AND

If this bit in the reference combination is taken into account when analyzing the received information, i.e. the value corresponding to the mask 1 bit, the pulse from the output of block 49, tested on the element I 17, passes to the input of the counter 50, increasing its state by one, otherwise the state of the counter 50 is not changed.

Counter 51 counts the number of single bits of the combination of the threshold number of matches, which, prostrobirovannye on the element And 19, passes

to the input of the counter 51 with the output of the fourth major element 48.

When exceeding the number coming from the output of the counter 50 to one of the inputs of the threshold element 52, the number

defined on its other inputs by counters 51, the output of threshold element 52 is a detection signal of a given code pattern. The invention allows to expand

the functionality of the device by allowing the operative change of the threshold number of matches of the received and reference combinations, the possibility of connecting the device to a microcomputer or microprocessor system and having a common bus interface, and the ability to access various reference combinations corresponding to them

masks and combinations of the threshold number of matches from among those stored in the accumulators, by entering the code of the initial address of the accumulators, a. also increase the reliability of the device by introducing majority elements and three independent regions of the memory in the cfd drive.

6f: 62

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J; 4f; 5

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Claims (1)

A LOGIC MEMORY DEVICE comprising a pulse generator, an OR element, a trigger, an address register, an address counter, first, second and third drives, a comparison unit, a first AND element, a hit count and a threshold element, the first trigger input connected to the first input of the OR element , the output of which is connected to the input of the address counter, the outputs of which are connected to the inputs of the address setting of the first drive, the information input of which is the first information input of the device, the address setting inputs of the second opitel connected to the installation inputs of the third drive, the output of the comparison unit is connected to the first input of the first element And, the output of which is connected to the input of the counter of the number of matches, the outputs of which are connected to one of the inputs of the threshold element, the output of which is the output of the device, characterized in that, with In order to increase the reliability of the device, a signal distributor, signal conditioners, pulse train former, second and third elements AND, elements NOT, an input address input unit, adder, mul are introduced into it typlexer, fourth drive, majority elements, counter of the threshold number of matches, and the output of the pulse generator is connected to the first input of the first signal conditioner and to the input of the signal distributor, the first output of which is connected to the first inputs of the second and third signal conditioner and the pulse shaper and the input of the first element NOT, the second input of the second signal conditioner is the synchronizing input of the device, the first output is connected to the first input of the trigger, and the second output to the second an ode to the third signal shaper, the output of which is connected to the second inputs of the first trigger and the burst driver, the first output of which is connected to the third inputs of the second and third signal shapers, and the second output to the second input of the OR element, the trigger output is connected to the first input of the second element And, the second input of which is connected to the output of the first element NOT, and the output to the control input of the first drive, the third output of the pulse shaper is connected to the first input of the adder, the second input of which connected to the output of the address register, the information input of which is connected to the information output of the input address input unit, the control output of which is connected to the second input of the first signal conditioning instrument, the output of which is connected to the control inputs of the address register and the input address input unit ', the information inputs of which are information the inputs of the second, third and fourth drives are the second information input of the device, and _(the address input is connected to the output of the second element NOT, the first input is multiplex sora is the address input of the device, the second input is connected to the output of the adder, and the output to the input settings of the address of the second, third and fourth drives, the control inputs of which, the control input of the multiplexer and the input of the second element are NOT the control input of the device, the outputs of the drives are connected to the inputs of the corresponding majority elements, the outputs of the first and second majority elements are connected respectively to the first and second inputs of the comparison block, the output of the third majority element is connected to the second the second input of the first AND element, the third input of which is connected to the second output of the signal distributor and the first input of the third AND element, the second input of which is connected to the output _{t of} the fourth majority element, and the output to the input of the counter of the threshold number of matches, the outputs of which are connected to another input of the threshold element.