SU1171785A1 - Device for calculating values of trigonometric functions - Google Patents

Abstract

DEVICE FOR COMPUTING trigonometric function comprising a shift register, a memory unit and three accumulators, the output of the shift register connected to the address input of the memory, the outputs of the first and second accumulators connected respectively with the first and second outputs of the device, the first information input of the third accumulator The adder is connected to the output of the shift register, characterized in that, in order to improve speed, the multiplier, analysis and blocking blocks are entered into it to the control, the outputs of the first and second multiplication units are connected to the first inputs of the first and second accumulating adders, respectively, the second inputs of which are connected to the outputs of the fourth and third multiplication units, respectively, the output of the first accumulating adder to the first inputs of the first and second multiplication units, the output of the second accumulating the adder is connected to the first inputs of the third and fourth multiplication units, the second inputs of the first and r-4f .. TC4. t the third multiplication units are connected to the first output of the memory unit, the second output of which is connected to the second inputs of the second and fourth multiplication units, the information input of the shift register and the second information input of the third accumulating adder are connected to the inputs of the corresponding constants of the device, and the analysis unit contains a register , subtractor, trigger, two groups of elements OR, three groups of elements AND, two elements AND, element NOT, element G1NY-NOT and element OR, the output of the element is NOT connected to the first inputs of the first &Amp;amp; the first and second elements of the I, which are connected to the first and second inputs of the trigger, the direct and inverse outputs of which are connected to the first inputs of the elements And respectively the first and second groups, the second inputs of the elements And which are connected to the output of the element NOT, the outputs of the elements And from the first to the third groups are connected to the corresponding inputs of the corresponding elements OR of the first group, 00 whose outputs are connected to the first information input of the subtractor, the output and the second information input of which are connected to the corresponding But with the information input and output of the register, the installation input of which is connected to the outputs of the OR elements of the second group, the output of the register sign is connected to the first input of the OR element, the second input of which is connected to the output of the SHSh-NOT element, the inputs are connected to the register output, the first and second the inputs of the elements And the third group are connected with the output, respectively, of the shift register and input

Description

home mode setting device connected to the input element is NOT, the third inputs of the elements of the first and second groups are connected respectively to the second and first outputs of the memory block, the inputs of the elements OR of the second group are connected to the inputs of the sine, cosine and argument of the device, respectively, the second inputs of the first and the second elements And are connected respectively to the inputs of the sine and cosine of the device, wherein the control unit contains five triggers, two NOT elements, four OR elements and nine AND elements, and in the control unit the output The first element is NOT connected to the first inputs of the first to fourth element AND, the first element OR is connected to the first input of the fifth and second input of the first element AND, whose outputs are connected to the first inputs of the second and third elements respectively, the outputs of which are connected to the inputs respectively, the first and serially connected second, third and fourth flip-flops, the output of the first flip-flop is connected to the first inputs of the sixth and seventh elements And, the outputs of KOTOpbtx are connected respectively to the first inputs s of the fourth OR element and the eighth AND element, whose input is connected to the second input of the third AND element, whose output is connected to the second input of the fourth OR element, the output and third input of which are connected respectively to the input of the fifth trigger and the ninth element output, And the first input which is connected to the output of the fourth trigger and the second input of the fourth element AND, the output of which is connected to the second input of the second element OR, the output of the second element is NOT connected to the second input of the sixth element AND, the output of the fifth trigger ra is connected to the first input of the first element OR, the output of the third element AND is connected to the second input of the second element AND, the output of the eighth element AND is connected to the second input of the third element OR, the input. the device mode settings are connected to the input of the first element NOT and the second inputs of the fifth, eighth and ninth elements AND the control unit, the input of the second element NOT and the second input of the seventh element AND the control unit are connected to the output of the OR element of the analysis unit, the second input of the second element The OR control unit is connected to the device start input, the outputs of the third element OR and the fifth trigger of the control unit are connected to the control input of the subtractor of the analysis unit, the outputs of the second element AND, the second element OR, and the sixth element And a control unit connected with the control inputs of the shift register, respectively, of the third accumulator and the memory unit.

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The invention relates to the field of automation and computing and can be used in arithmetic logic devices of computing systems for various purposes in the hardware implementation of the calculations of trigonometric functions.

The aim of the invention is to increase speed.

Figure 1 presents the block diagram of the device; Figures 2 to 4 are block diagrams of an analysis block, a multiplication block (matrix type) and a control block, respectively.

The device contains a memory block 1, blocks 2.1 - 2.4 multiplying, accumulating paths 3.1 - 3.3, a shift register 4, an analysis block 5 and a control block 6.

The analysis block contains a register 7, a subtractor 8, a trigger 9, a group of elements OR 10.1 to 10.2, elements AND 11.1 to 11.2, an element NOT 12, a group of elements AND 13, a group of elements AND 14.1 to 14.2, an element OR-NOT 15 and an element OR 16 .

The matrix multiplier contains the elements And 17 and adders 18.

The control unit contains triggers 19.1–19.5, elements AND 20.1–20.9, elements OR 21.1–21.4, and elements NOT 22.1–22.3. 31 The device allows simultaneous computation of direct trigonometric functions sin b and cos b or inverse arcsinx and arccosx. For their calculation, you use sin (oi} + y;) sino..cos y. ++ cosci sin j, -; COS (eij.T +,.) 3 ,. - ,, siny,.,, -. 1 (1) where oi-i Z jti / | (Richem (2) r with y 1. oill) with y 0; (3), .. L 1 with / 3j H, -. (4) 1 ° when (.,; Ai is the value of the basic MS., - / 5f ANGLES in radians: x: with Y 1 with y and, with i 1,1,3, ..., 15. When calculating the inverse trigonometric functions directly determine the value of only one function arcsin (arccos x), then, using the arccos X - - srcsin x ratio, we determine the value of another function. Consider the operation of the device for calculating the sine and cosine values of the angle 0, also represented in radians At the initial time, the binary register code 4 ((9 45)) is supplied to the shift register 4, the binary A code The angle code is recorded as 4–6, whose sine and cosine values are to be calculated, the first and third accumulating adders 3 record the zero code (sin (ic sin O 0), and the second accumulator ad 3 in the second accumulator 3 ), the mode I is set (Calculation of direct trigonometric functions), which is fed to the seventh input of the analysis unit 5 and the third input of the control unit 6, and the Start signal is received to the second input of the control unit 6. The value of g (in the first iteration / b - g) is fed to the first input of analysis block 5, where the signal from the first output of control block 6 is the verification of condition (4). If this condition is fulfilled, then from the code 854 of the analysis block 5, a signal is sent to the control block 6 and by a signal from the third output of the latter, arriving at the control input of the memory block 1, the address input of which simultaneously receives the code f from the output shift register 4, simultaneous readings of sin j are performed. and cos are fed to the first inputs of the respective multiplication units 2. A bit of the read signal in memory block 1 is equivalent to the operation y; / 9), and its absence - the operation jpj .0, which corresponds to the expression (3). At the same time with. checking the wave condition of conditions (4) in block 5 of the analysis, the next value of the angle V is calculated by expression (5). In blocks 2 of multiplication (matrix type), the second inputs of which receive the values of the sines and cosines of the corners, respectively, which are calculated in the (i - 1) -th iteration, form the product sinai.cos y, co8a siny, coso / .cos jj and sinij-sin ji ,. The resulting products are received in pairs, respectively, at the first and second inputs of the first and second adders, respectively, where the value of the next approximation sin b and cos b is formed. Then, from the fifth output of the control unit 6 to the shift register 4, the shift signal is released and its contents are shifted one bit to the right, i.e. the next base angle j is formed. If condition (4) is not satisfied, then the signal from the output of the analysis unit 5 to the input of the control unit 6 is not input. According to the signal coming from the second. The PIR output of the control unit, in block 5 of the analysis, the value of V 1 is formed in accordance with the expression (5), the read signal in block 1 of the memory does not make that it corresponds to (0. Values: the first and second accumulating adders 3 do not change , and only the shift register 4 is shifted (the formation of the next value of the base angle). This process is repeated i times (i 1, 2, ..., 15). Consequently, if condition (4) is not satisfied, then the cycle The executions in this iteration are reduced by a time equal to the time taken to read from the memory, file product and sum. In calculating inverse functions (arcsin X and arccos x), the initial states of all blocks are the same as in calculating direct functions. Device operation corresponds to operation when condition (4) is fulfilled with the exception of the following. Signal Mode on the corresponding inputs of the analysis and control units 5 and 6, respectively, are not received, and the direct code sin enters the fourth (fifth) input of the analysis unit 5 as the initial data. X (the additional code is cos x), and its third (second) input is the direct sine code of the base angle sin / 3 (the additional cosine code of the base angle cos / Y), and angle 1. is fed to the input of the third accumulating adder 3. The Start signal from the third output of the control unit 6 is outputted to the memory unit 1, and the sin / 3 values are read. cos ft. which are received in the corresponding code to the corresponding external inputs of the analysis block 5. In the latter, according to the signal emitted from the first output of the block, the following condition is fulfilled analogously to pressing (4): sin / 5, sinV .., 1 at I cos, in; cos4 {.V / account G sin / 5i sin with 1 ,,, I cos / i | cos H-d, where sin /}, - (cos /) is calculated by expressions (2), and s ;; , sin V. (8) 1 sin Y .., with, i 1, 2.,., 15. If condition (7) is fulfilled, then a signal is output from the output of the analysis block 5 to the first input of the control block 6, and its fourth output gives a signal to the input of the third accumulating adder 3, according to which the next i-th base angle is added to the contents of the adder. If condition (7) is not fulfilled, then signals from the output of the analysis unit 5 and the fourth output of the control unit 6 are not output and the contents of the third accumulating adder 3 do not change. This is equivalent to performing the following arcsin X - Zl-y;) with) - ™. . J 1. . where y-, is determined by the expression. Then, the contents of the shift register 4 are shifted and the calculation process is repeated. If, when calculating one inverse function, it is necessary to simultaneously calculate the value of another, then after issuing the value of the angle B of the first function, the additional input of the third accumulating adder 3 receives the code where the calculation is made using the expression (6) and issuing the angle value of the other function. The maximum value of the angle, which can be fixed by the third accumulating adder 3, must be equal to / (90 °). .

Claims (1)

DEVICE FOR CALCULATING TRIGONOMETRIC FUNCTIONS, comprising a shift register, a memory unit and three accumulating adders, the output of the shift register being connected to the address input of the memory unit, the outputs of the first and second accumulating adders connected respectively to the first and second outputs of the device, the first information input of the third accumulating adder with a shift register output, characterized in that, in order to improve performance, four multiplication blocks, an analysis block, and a control block are introduced into it The outputs of the first and second multiplication units are connected to the first inputs of the first and second accumulating adders respectively, the second inputs of which are connected to the outputs of the fourth and third multiplying units, respectively, the output of the first accumulating adder is connected to the first inputs of the first and second multiplying units, the output of the second accumulating adder connected to the first inputs of the third and fourth blocks of multiplication, the second inputs of the first and third blocks of multiplication are connected to the first output of the memory block, the second the output of which is connected to the second inputs of the second and fourth blocks of multiplication, the information input of the shift register and the second information input of the third accumulating adder are connected to the inputs of the corresponding constants of the device, and the analysis unit contains a register, a subtractor, a trigger, two groups of OR elements, three groups of AND elements, two AND elements, an NOT element, an OR-HE element and an OR element, the output of the element is NOT connected to the first inputs of the first and second AND elements, whose outputs are connected to the first and second inputs of the trigger RA, the direct and inverse outputs of which are connected to the first inputs of AND elements of the first and second groups, the second inputs of AND elements are connected to the output of the element NOT, the outputs of AND elements from the first to third groups are connected to the corresponding inputs of the corresponding OR elements of the first group, outputs which are connected to the first information input of the subtractor, the output and the second information input of which are connected respectively to the information input and the output of the register, the installation input of which is connected to the electronic outputs OR of the second group, the output of the register sign is connected to the first input of the OR element, the second input of which is connected to the output of the OR-HE element, the inputs of which are connected to the output of the register, the first and second inputs of the elements of the third group are connected to the output of the shift register and input respectively11171785 setting the device mode, connected to the input of the element NOT, the third inputs of the AND elements of the first and second groups are connected respectively to the second and first outputs of the memory block, the inputs of the OR elements of the second group are connected to the inputs, respectively essentially the sine, cosine, and argument of the device, the second inputs of the first and second elements of AND are connected respectively to the inputs of the sine and cosine of the device, while the control unit contains five triggers, two NOT elements, four OR elements, and nine AND elements, and the output of the first element is NOT connected to the first inputs from the first to fourth elements AND, the output of the first element OR is connected to the first input of the fifth and second input, the first elements AND, the outputs of which are connected to the first inputs, respectively, of the second and the third OR element, the outputs of which are connected to the inputs of the first and sequentially connected second, third and fourth triggers, the output of the first trigger is connected to the first inputs of the sixth and seventh AND elements, the outputs of which are connected respectively to the first inputs of the fourth OR element and the eighth AND element, the input of which is connected to the second input of the third AND element, the output of which is connected to the second input of the fourth OR element, the output and third input of which are connected respectively to the input of the fifth trigger and the output of the ninth element And, the first input of which is connected to the output of the fourth trigger and the second input of the fourth element And, the output of which is connected to the second input of the second element OR, the output of the second element is NOT connected to the second input of the sixth element And, the output of the fifth trigger is connected to the first the input of the first OR element, the output of the third AND element is connected to the second input of the second AND element, the output of the eighth element AND is connected to the second input of the third OR element, the input of the device mode setting is connected to the input of the first element NOT and the second inputs of the fifth, eighth and ninth elements AND control unit, the input of the second element and the second input of the seventh element AND control unit are connected to the output of the OR element of the analysis unit, the second input of the second OR element of the control unit is connected to the start input of the device, the outputs of the third the OR element and the fifth trigger of the control unit are connected to the control input of the subtractor of the analysis unit, the outputs of the second AND element, the second OR element and the sixth element of the control unit are connected to the control inputs respectively of a shift register, the third memory block accumulating to the adders.