SU1171756A1 - Digital extrema pointer - Google Patents

Abstract

DIGITAL EXTREME INDEX, containing a clock pulse generator, a comparator, four 2I elements, a reversible counter, a D / A converter with an additional bit and an EZ flip-flop, the first inputs of the 2I elements are interconnected, the outputs of the first and second elements 2I are connected to summation and the subtracting inputs reversible counter, the outputs of which are connected to the inputs of the basics of the bits of the digital-to-analog converter, whose output is connected to the first input of the comparator, the second input D which is connected to the input signal bus, characterized in that, in order to increase its reliability in operation and expand the field of application, a D-trigger, a single-oscillator and two counting triggers are introduced into it, the information D-trigger being connected to the comparator output, the synchronization input - with the output of the clock pulse generator and the input of the one-shot, the output of which is connected to the first inputs of the 2I elements and the inputs of the first and second snappy triggers whose outputs are connected respectively to the second inputs of the third and fourth elements 2I, outputs to (L toykh are connected to the inputs of the RS-trigger, direct output of the D-trigger is connected to the input of the additional bit of the D / A converter, with the second input of the first element 2I and the installation input zero of the first counting trigger, and the inverse output D -trigger connected to the second input of the second element 2I and the installation of the installation zero of the second counting trigger. SP and

Description

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The invention relates to digital instrumentation technology and Knife to be used in automatic control systems to determine the extreme values of analog signals.

The purpose of the invention is to increase the reliability of the device and expand the scope.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 - the process of determining extremes and signal plots at different points of the device, which reduce the principle of operation. ,

The device contains a generator of 1 clock pulses, comparator 2, first 3, second 4, third 5 and quarter 6 elements 2I, reversible counter 7, digital-to-analog converter 8, P5 flip-flop 9, D-flip-flop 10, one-shot 11 and the first 12 and second 13 counting triggers. Output buses 14 and 15, Min and Max devices, respectively, the input signal bus 16, the additional increment 17 of the balancing signal, the levels of 18-20 quantization of the balancing signal, the signal 21 at the output of the clock generator, the signal 22 at the output of the one-oscillator, the signal 23 at the direct output of the D trigger, the signal 24 at the inverse output of the D-flip-flop, the signal 25 at SuF1Tecuting input of the reversible counter, the signal 26 at the subtractive input of the reversing counter, the signal 27 at the output of element 2I 5, the signal 28 at the output of element 2I 6, si nal 29 on output line 14 Min device; signal 30 on the output bus Max 15 device.

The device works as follows.

The device is based on the method of determining the extremum by changing the sign of the derivative of an analog signal when it passes its extreme value by determining the moment of changing the sign of the increment of the balancing signal with a subsequent analog-to-digital conversion of the input signal. The input signal from the bus 16 is fed to the input of the single-threshold comparator 2, to the other input of which a balanced signal is output from the output of the digital-to-analog converter 8

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(Fig. 1) The output signal of the comparator 2 is fed to the information input of the 15-flip-flop 10, which is synchronized by the front of the pulses coming from the output of the generator 1 clock pulses. Thus, the output signal of the comparator 2 at the time of filing the next clock pulse is memorized at the forward output of the D-trigger 10 for a time equal to the period of the clock pulses. The direct and inverse outputs of the trigger 10 are connected, respectively, to the inputs of elements 2 and 3 and 4, to the other inputs of which counting pulses are output from the output of the single vibrator 11 delayed relative to the clock ones, since the single vibrator 11 triggers according to the decay of the pulses of pulses (plots 21 and 22, Fig. 2) .. /

Depending on the state of the outputs of the D-trigger, the counting pulses are fed to the summing or subtracting inputs of the reversing counter 7 in such a way that the balancing signal from the output of the D / A converter 8 monitors the change in the input signal. The device uses a single-threshold comparator, so if the difference between the input and balancing signals does not exceed the value corresponding to a single increment of the balancing signal, an oscillatory tracking process is established. the value of the input signal (figure 2). The tracking process is characterized by the fact that the summing and subtracting inputs of the reversible counter in turn receive one counting pulse until the value of the input signal becomes greater or less than the neighboring levels of quantization of the balancing signal. As soon as this happens, the counting or subtracting inputs of the reversible counter receive two counting pulses, which indicates an increase or decrease in the input signal, respectively. For example, if the value of the input signal is between the quantization levels 19 and 20 (Fig. 2), then before the arrival of the sixth counting pulse, the balance signal value fluctuates relative to the input signal. After being converted to the input level of 19 quantization oscillator3

The violated process is disrupted and the sixth counting pulse is fed to the summing INPUT) of the reversible counter, which is the second order (Diagram 2.3 and 25, Fig. 2). The same situation develops at the moment of arrival of the ninth counting pulse, after the value of the input signal exceeds the level of 18 quantization. When the input signal size becomes less than the 18 quantization level, the reversible counter input receives seventeen counts impulses, which is the second subtraction (plots 24 and 26), the same situation develops at the moment of the arrival of the twenty-second counts pulse.

Allocation of the second and subsequent pulses to one another at one of the inputs of the reversible counter and determining the type of extremum is carried out by a circuit containing counting triggers 12 and 13, elements 2 and 5 and 6, and R5 trigger 9. The circuit works as follows.

The counting inputs of the flip-flops 12 and 13, as well as the first inputs of elements 2 and 5 and 6, receive counting broad pulses from the output of the one-shot 11 (plot 22). Suppose that at the initial moment of time the counting pulses are absent at the direct output of the iD-flip-flop signal with the level of a logical unit, and at the inverse output there is a signal with the level of logic zero, which corresponds to the state before the arrival of, for example, the fifth counting pulse on the plot 22. Let us also assume that before this the triggers 12 and 13 were reset to zero and at their direct outputs - from 1 signal with a logic zero level. And a counting pulse with a level of logical units has appeared. A drop of this pulse triggers trigger 12 and a signal appears at its direct output with a level of logic one, but already after that, a counted pulse is removed from the input of element 2 and 5. Therefore, the output state of element 2 and 5 does not change and corresponds to a signal with a logic zero level (plot 27) At this, trigger 13 is zero. Thus, after passing the first counting pulse, element 2I 5 is prepared for the arrival of the second counting pulse

the course of element 2 and 5, if trigger 12 is not reset, i.e. if the D-trigger 10 does not change its state after the passage of the first counting pulse. In this case, the second counting pulse (plot 27) is fed to the input of the RS flip-flop 9 and the level of the logical unit (plot 29) is recorded on the output bus Min 14 of the device. The scheme works similarly when changing the signal levels at the outputs of B-flip-flop 10, but the pulses appear at the output of element 2 and 6 (plot 28), and the level of the logical unit is fixed to the output bus Max 15 of the device (plot 30).

In order to eliminate malfunctions with an exact equality of the input signal to the level of quantization of the balancing signal and to ensure an unambiguous transition of this level, positive feedback was introduced into the device using an additional digital-to-analog converter controlled by a signal with My exit D-flip-flop. The leading positive feedback from the comparator output to its input, applied in the proposed device, differs from the usual positive feedback, created by the comparator hysteresis in that the necessary additional increment 17 (Fig. 2) does not receive the counterbalance signal at the moment of excess over the input signal. earlier, when, after the next clock pulse is applied to the D-flip-flop synchronization input, the signal at its direct output allows the passage of

This is done, for example, when the third clock pulse is fed to the synchronization input of the D trigger (plots 21, 23 and 25).

Thus, in the proposed device, the insensitivity zone value is always equal to the differences in the two adjacent levels of the quantization of the balancing signal, and therefore the influence of the nonlinearity of the conversion characteristics of the digital-to-analog converter on the extremum determination process is excluded. This allows using the balancing signal, in which the increment value can be monotonously vary according to any law. The deadband and a single increment of the balancing signal are therefore, in the proposed device there is no special shaper of the deadband, made, for example, in the form of a two-threshold comparison device or an additional discharge of a digital-analog converter, as in the known devices, And this ensures stable operation. device and its reliability. Compared to the known device, the likelihood of malfunctioning or total failure under the influence of destabilizing factors (change in ambient temperature, instability of supply voltages, aging of elements, etc.) is substantially reduced. This is because in order to preserve the operability of the proposed device, it is sufficient to ensure the minimum necessary sensitivity of the comparator and the monotony of the conversion characteristics of the digital-to-analog converter. In the known device, besides, is required. For this purpose, to ensure the stability of the deadband, the linearity of the conversion characteristic and the constancy of the ratio of the magnitude of the deadband and the single increment of the balancing signal, which is complex and does not always guarantee reliable operation of the device. And for automatic control systems, maintaining performance is more important, even if with a slight deterioration in accuracy. In the proposed device, a coherently reliable control circuit for an additional bit and a reversible counter without the use of short pulses, the duration of which is commensurate with the operating time of logic elements, is logically reliable. This increases the reliability of the device and makes it insensitive to the variation of the parameters of elements. The introduction of pre-storing the result of cf. incoming and counterbalancing signals using the 1-trigger does not only not reduce the speed of the device, but, on the contrary, allows the use of gated comparators with significantly higher speed. The application of the proposed device in automatic optimization systems significantly expands their functionality, as it allows to adjust various signals with optimum accuracy to Optimum, the optimum values of which are not known beforehand, but only a range of possible values is known. This is achieved by using a non-linear digital-to-analog converter in the device, in which the output signal increment increases with this signal. A linear converter with a non-linear element, such as a diode, can also be used at the output. In contrast to the known device in the proposed device, it is possible to carry out continuous performance monitoring by the presence of an oscillatory tracking process, which takes place only when the analog-digital converter is operational. In the known device, the modified input signal, there is no information on the health of the reversible counter. The advantage of the proposed device is to reduce the cost of development and manufacture due to the possibility of using serial elements with low stability parameters. According to the proposed technical solution, a layout of the device was made, in which chips of 133 series, BUT and 265 were used. The device is included in the system of automatic optimization of the output power of the amplifier and allows adjustment with a constant accuracy of 5% when the possible value of the optimal power is changed 15 times. Testing of the layout showed reliable, without failure), the operation of the device in a wide range of temperature changes and supply voltages.

Claims (1)

A DIGITAL EXTREMUM INDEX containing a clock • generator, a comparator, four 2I elements, a reverse counter, a digital-to-analog converter with an additional bit and RS ^ Tpurrep, with the first inputs of 2I elements connected to each other, the outputs of the first and second 2I elements connected to the summing and subtracting the inputs of the reversible counter, the outputs of which are connected to the inputs of the main bits of the digital-to-analog converter, the output of which is connected to the first input of the comparator, the second input of which is dinen with an input signal bus, characterized in that, in order to increase its reliability in operation and expand the scope, a D-flip-flop, a one-shot and two counting flip-flops are introduced into it, and the information input of the D-flip-flop is connected to the comparator output, the synchronization input with the output of the clock pulse generator and the input of a single vibrator, the output of which is connected to the first inputs of the elements 2I and the inputs of the first and second counting triggers, the outputs of which are connected respectively with the second inputs of the third and fourth elements 2I, the outputs of which are connected to the inputs of the RS-flip-flop, the direct output of the Г-flip-flop is connected to the input of the additional discharge of the digital-analog converter, with the second input of the first element 2I and the input for setting the zero of the first counting trigger, and the inverse output of the D-flip-flop is connected to the second input of the second element 2I and the zero input of the second counting trigger. 1171