SU1167605A1 - Calculating device - Google Patents

Abstract

A COMPUTING DEVICE containing a register of a number, a character trigger, a control unit and an adder, the information output of the adder is connected to the information input of the number register, the output of the number register is connected to the first group of inputs of the totalizer, the output of the higher digit register of the number is connected to the input of the trigger sign , characterized in that, in order to reduce the amount of equipment and enhance functionality by providing the possibility of squaring it, A binary reversible counter is entered, the outputs of the binary reversing counter are connected to the second group of inputs of the adder-subtractor, starting with the penultimate last digit, and the control unit contains a micro-command register, four decoders, four AND elements, an OR-NOT element, four 2-2 AND- elements OR, microcommand address register, firmware memory, OR element, start trigger, pulse generator, control counter, the outputs of the first three bits of the microcommand register are connected to the input of the first decoder, output the fourth and fifth order bits of the micro-command register are connected to the inputs of the second decoder, the outputs of the tenth and eleventh bits of the micro-command register are connected to the inputs of the third decoder, the output bits of the micro-command register from the twelfth to the fifteenth are connected to the first inputs of the first, second, second and third respectively the fourth elements 2-2 and-OR, the outputs of the bits of the register of the micro-command from the sixteenth to the nineteenth are connected to the second inputs, respectively (L of the first, second, third and fourth elements tde 2-2I-OR, first, second and third outputs of the third decoder are connected to the first inputs of the first, second and third elements AND, respectively, the outputs of the first, second and third elements AND are connected respectively to the first, second and third elements of the OR- NOT, direct output of Element OR-HF. 9) LED is connected to the third inputs of the first, second, third and fourth elements 2-2И-OR, and the inverse output of the element OR-NOT connected to the fourth inputs of the first, second, third and fourth elements 2-2 AND-OR, the outputs of elements 2- 2И-Ш1И are connected to the inputs of the corresponding bits of the microcommand address register, the outputs of the bits of the register of the microcommand address register are connected to the corresponding bits of the microprogram memory address input, bits of the information.

Description

firmware memory output is connected to the corresponding bits of the microcommand register information input, the fourth port of the first decoder is connected to the first input of the OR element, the seventh output of the first decoder is connected to the second input of the OR element, the output of the OR element is connected to the reset trigger start input, the trigger trigger output connected to the first input of the fourth element And, to the second input of the fourth element And connected to the output of the pulse generator, the output of the fourth element And is connected to the input of the control counter The information outputs of the control counter are connected to the inputs of the fourth decoder, the first output of the fourth decoder is connected to the NMCponporpaMM memory synchronization control input, the second output of the fourth decoder is connected to the control input of the microcontrol register, the third output of the decoder is a switch. microcommand addresses, the first output of the first decoder is connected to the control input by entering the number register information, the first output of the second decoder dklyuchen to the reset input of a binary down counter and the second output of the first decoder connected to the input control vschachey informatsgi

the number register, the second output of the second decoder is connected to the control input of the information of the binary reversible counter, the output of the sixth bit of the micro-command register is connected to the control to the input of the second adder's information, the seventh-bit register of the micro-command is connected to the low-power bit of the second group of the adder's matcher subtractor, the output of the eighth bit of the microcommand register is connected to the control input of the subtractive mode subtraction mode setting, the third output of the first decoder is connected to The increment input of the binary reversible counter, the fifth output of the first decoder, is connected to the reset control input of the number register, the third output of the second decoder is connected to the input input control input to the binary reversal counter, the sixth output of the first decoder is connected to the output of the binary reverse counter, the output of the second decoder is connected to the output of the binary reverse counter, the output of the second decoder is connected to the output of the binary reverse counter, the output of the second decoder is connected to the output of the binary reverse counter, the output of the second decoder is connected to the output of the binary reverse counter, the output of the second decoder is connected to the output of the binary reverse counter, the output of the second decoder is connected to the output of the binary reverse counter, the output of the second decoder is connected to the output of the binary reverse counter, the output of the second decoder is connected to the output of the binary reverse counter, the output of the second decryptor Yes, the microcommand register is connected to the control input of the summation mode of the adder reader, the output of the sign trigger is connected to the second input of the second el ment And, the overflow output of a binary up-down counter connected to the second input of the third element I.

The invention relates to digital computing and is intended for use in the development of hardware and software of digital computers. The aim of the invention is to reduce the number of equipment, increase speed and enhance the functionality of the device by providing the possibility of squaring. In FIG. 1 is a block diagram of a computing device; Figures 2 and 3 are respectively a functional diagram of the device control unit and the firmware of the device. The device contains a register of 1 number, a trigger 2 characters, adder-subtractor 3, a binary reversible counter 4 and a control unit 5. The control unit 5 contains a register 6 micro-commands, decoders 7-10, the element OR 11, the trigger 12 start, the element ШИИ-НЕ 13, elements 14-14, pulse generator 18, control counter 19, elements 2-2 and 20-23, microcommand address register 24, microprogram memory 25. In the device, a sequence of odd numbers is formed from the natural number of numbers obtained on binary reversible counter, by the fact that the input is younger The subtractor is always a one. An example of the formation of a sequence of odd numbers is given in Table. 1. The device operates in two modes: in square root mode and in square mode. The initial state of the device in the square root extraction mode, the number from which the square root is to be extracted is placed in register 1, the reversible counter 4 is in the zero state. The signal from the control unit 5 on the adder-subtractor 3 subtracts from the contents of register 1 the contents of the binary reversible counter 4 and the unit in the low-order bit. The result of the subtraction is placed back into register 1. If trigger 2 of the number character retains its initial value, then the unit (increment) is added to the contents of reversing counter 4 by a signal from control unit 5 and the process repeats until control unit 5 records a state change of three hera 2 digits of the number, after which it stops the calculation process. The content of the reversible counter 4 is the result of extracting the square root of the whole number. An example of the extraction of the square root from the number 25 is given in Table 2 (PC 4 is a reversible counter 4). The calculation process stops at the sixth step. The content of the reversing counter 4 is (0101) 5. The initial state of the device in squaring mode: the number to be squared is placed in a binary reversible counter 4, which, when squaring works in - in the unit subtraction mode, register 1 is in the zero state. The signal from the control unit 5 from the counter 4 subtracts the unit (decrement), the adder 3 and the addr 3 add the contents of the register 1 and the contents of the counter 4 and the units applied to the inputs of the adder 3. The result of the addition is recorded in the re 054 gist 1, The repetition of the micro decrements of the decrement of the 4 addition counter is performed before the counter 4 overflows, the signal of which, coming from the higher bit to the control unit 5, stops the process of calculating the square number. After the control unit 5 has fixed the overflow of the counter 4, the addition is not performed. The result of the calculation is in register G. An example of squaring the number 5 is given in Table. 3. In table. 3 The following notation is accepted: WG 1 - register 1; PC 4 - reversible counter 4; DK - PC 4 decrement; P- - no PC 4 overflow; P + - the presence of PC 4 overflow; ZM - the addition of the contents of the WP 1 s. PC 4. The result on PC 1 is (11001). The control unit of the device is implemented according to the principle of an automaton with programmable logic (Fig. 2). It produces control signals Y, -Y, 4. in accordance with the firmware of the device (Fig. 3), where X, X and Xj are awareness signals with eating meaning: X, 1 in the case of extracting the square root; X O in the case of squaring; X. | 1 in the case of setting the sign trigger of the number to one; Xj O in the case where the sign trigger of the number is in the zero state; Xd 1 in the event of a binary reversible counter overflow signal; X5 O in the absence of an overflow signal of a binary reversible counter; Y - 4 control signals, under the influence of which the following microoperations in the device are realized; Y is the entry in the register of the number of the original number; Y — set the reversible counter to the zero state; Y - transfer of the code register number to the first input of the adder-subtractor; 5 J - transfer of the code of the reversible counter to the second input of the totalizer; V5 is the input of the code of the adder-calculator to the input of the register of the number; Yg is the signal for supplying the unit to the input of the lower bit of the adder — you are the reader; Yj - task mode Subtraction adder-subtractor; Od - an increase in the content of the reverse counter by one; Ul- - view of the contents of the reversing counter; XK - setting the number register to the zero state; Y, - entry in the reversible count of the original number; . reducing the contents of the bill by one; Y - the contents of the register number; yt4 - setting the mode Addition of the adder-subtractor. The operational part of the microcommand is divided into five fields of a length of 3, 2, 1, 1.2 bits, respectively. For each sex, the microoperations are encoded as follows: A zero value of the floor indicates the absence of micro1Uoperations. 5 The address part of the microcommand contains 10 bits and is built on the principle of forced addressing with two addresses. The field of awareness signals contains 2 bits and is encoded as follows: 01 - X 1; 10- Xj 1; 11-X, .j 1. A value of 00 indicates a zero value of the alert signals. Tab. 4 is a table of firmware for the control unit firmware. In tab. 4, the X symbol indicates the indifferent code value of the gender of the microcommand. The control unit shown in FIG. 2, works as follows. In the initial state, the micro-command register, the micro-command address register, the control counter and the trigger start are reset. The start trigger trigger signal is set to one, the pulses from the pulse generator through the element 17 are fed to the input of the control counter; Time-distributed signals - TGs from the decoder 10 code ensure synchronous operation of the control unit in the following sequence: reads microcommands from the MSD (2), writes it to the microcommand register (Z), writes the address of the next microcommand into the microaddress address register CZ,). The deshufflers 7 and 8 are used to decode the V and Vg fields of the operational part of the microcommand. The operation of the control unit is stopped by resetting the trigger trigger to the zero state through the element OR 11 in the presence of micro-operations V or V (,.

Table 1

Table 3

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Claims (1)

A COMPUTER DEVICE containing a number register, a sign trigger, a control unit and an adder, the information output of the adder-subtractor is connected to the information input of the number register, the output of the number register is connected to the first group of inputs of the adder, the output of the high order digit register is connected to the setting of the sign trigger, characterized in that, in order to reduce the number of equipment and expand the functionality by providing the possibility of squaring, it introduced a binary reversible counter, the outputs of a binary reversible counter connected to the second group of inputs of the adder-subtracter, starting from the penultimate digit, the control unit containing a microcommand register, four decoders, four elements AND, an element OR, four elements 2-2 AND-OR , the micro-command address register, firmware memory, OR element, start trigger, pulse generator, control counter, and the outputs of the first three bits of the micro-command register are connected to the input of the first decoder, the outputs of the fourth and micro-register register bits are connected to the inputs of the second decoder, the tenth and eleventh micro-register register bits are connected to the inputs of the third decoder, the micro-command register bits outputs from the twelfth to fifteenth are connected to the first inputs of the first, second, third and fourth elements 2-2I-OR, respectively the outputs of the bits of the microcommand register from sixteenth to nineteenth are connected to the second inputs of the first, second, third and fourth elements 2-2I-OR, respectively, the first, sec the first and third outputs of the third decoder are connected to the first inputs of the first, second and third elements AND, respectively, the outputs of the first, second and third elements AND are connected respectively to the first, second and third inputs of the OR-NOT element, the direct output of the OR-NOT element is connected to the third the inputs of the first, second, third and fourth elements 2-2I-OR, and the inverse output of the OR-NOT element is connected to the fourth inputs of the first, second, third and fourth elements 2-2I-OR, the outputs of the elements 2-2I-OR S09Z9H are connected to the inputs of the corresponding bits of the register of the micro instruction address, the outputs of the bits of the register of the address of the micro instruction are connected to the corresponding bits of the address input of the firmware memory, the bits of the information output of the memory of the micro instruction are connected, the fourth input of the first decoder 'is connected to the first input of the element OR, the seventh output of the first decoder is connected to the second input of the OR element, the output of the OR element is connected to the reset input of the trigger p SKA, the trigger trigger output is connected to the first input of the fourth element And, the pulse generator output is connected to the second input of the fourth element And, the output of the fourth element And is connected to the input of the control counter, the information outputs of the control counter are connected to the inputs of the fourth decoder, the first output of the fourth decoder is connected to the control input of the microprogram memory synchronization, the second output of the fourth decoder is connected to the control input of the micro command register entry, the third output of the fourth decoder the torus is connected to the control input of the micro address register register, the first output of the first decoder is connected to the input control input of the number register, the first output of the second decoder is connected to the reset input of the binary reversible counter, the second output of the first decoder is connected to the control input of the output of the number register, the second the output of the second decoder is connected to the input of the information output of the binary reversible counter, the output of the sixth digit of the register of the microcommand is connected n to the control input of the adder-subtractor information output, the output of the seventh bit of the microcommand register is connected to the least significant bit of the second group of inputs of the adder-subtracter, the output of the eighth bit of the microcommand register is connected to the control input of the job of the subtraction mode of the adder-subtracter, the third output of the first decoder is connected to the increment input binary reverse counter, the fifth output of the first decoder is connected to the control input of the reset register number, the third output of the second decoder is connected to the input control of entering information into the binary reversible counter, the sixth output of the first decoder is connected to the decrement input of the binary reverse counter, the output of the ninth bit of the microcommand register is connected to the control input of the job of the summing mode of the adder-subtracter, the output of the sign trigger is connected to the second input of the second element And, the overflow output of the binary reversible counter · is connected to the second input of the third element I.