SU1167599A1 - Device for collecting and preprocessing information - Google Patents

Description

The invention relates to automation and computing and can be used in multi-level control systems containing local peripheral collection devices

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and information processing and managing

computing machine that performs the function of reducing parameters (for example, linearization)

and their analysis.

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A known device for collecting and processing information, containing N sensors connected to a switch, an interval sensor, a result counter and a control unit £ 1]. five

In this device, signaling (for example, frequency) sensors are converted over time by a single converter, which allows the use of the minimum number of communication lines, but this increases the cycle time for polling sensors and entering information into the control electronic computer. In addition, operations associated with the choice of 15 next sensor, as well as installation operations in the device are under the direct control of a computer. This reduces the efficiency of computer use and does not provide the possibility of autonomous operation of the device, which limits its functionality.

The closest to the invention is a device for collecting and primary processing information containing groups of sensors connected to the first inputs of a switching unit, a group of elements I, the first inputs of which are the first inputs of the switching unit and the outputs switching unit, and the switching element of the sensor, the first memory block, the control unit, a group of elements And, the outputs of which are connected to the first 35

the inputs of a group of counters and serially connected clock generator and synchronization unit. The device also contains a printing unit, an indication unit, an accumulation unit for reading the parameter value, and a unit for generating a three-parameter quadratic dependence (£ 2).

The disadvantage of this device is as follows. 45

As a rule, the object on which the sensors are installed is dispersed in space and is a set of technological equipment in the form of plants, machines, 50 units, etc., and the information processing from the sensors is concentrated in the electronic unit installed, for example, in the operator’s console .

When using the specified device, it is necessary to lay lines of communication from each subgroup of sensors (each technological unit

equipment) to the switching element (or from the switching element to the memory unit), which does not allow to reduce the number of these connections and thereby reduce the consumption of the transmitting cable.

Another significant disadvantage of this device is that it does not provide for the possibility of automatic control of the operation of blocks that carry out the transformation (primary processing) of information from higher-level devices (for example, computers). It reduces. functionality. and, in addition, reduces the reliability of the entire system (for example, an object management system), since the incorrect functioning of these units can · lead to incorrect functioning of the entire system.

The aim of the invention is to enhance the functionality by conducting a survey of frequency, two-position and encoded sensors and improving the reliability of work.

This goal is achieved by the fact that the device for collecting and preprocessing information containing a sensor switching unit, the information inputs of which are the information inputs of the device, the first memory block, the control unit, the elements AND, the output of each of which is connected to the counting input of the corresponding counter, generator clock pulses, the first output of which is connected to the information input of the synchronization unit, the second memory block, interval setting block, command counter, registers and multiplexer, input are entered The input inputs of which are connected respectively to the information outputs of the sensor switching unit, the address input of the multiplexer is connected to the address output of the first memory block, the clock inputs of the multiplexer and the interval setting block are connected to the second output of the clock generator, the outputs of the multiplexer are connected respectively to the information inputs of the registers and to the first inputs And elements, the second inputs of which and the permissive input of the interval setting block are connected to the permissive output of the control block Oia, the third inputs of the elements And

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connected, respectively, to the enabling outputs of the interval setting unit, whose information input, the first information input of the second memory block and the switching enable input of the switching unit mutation are connected to the information output of the first memory block, whose command output is connected to the command input of the unit pack, 0

The outputs for setting the initial state of which are connected to the installation inputs of counters, registers and command counters, the write input of the second memory block is connected to the output, the write permission of the control unit ^{, 5} register write inputs are connected respectively to the write outputs of the control unit, the meter reading inputs are connected to the outputs of the read control unit, an output razre- sheniya θ ² which is connected to the read registers registers reading inputs, the output of the first clock synchronization unit is connected to the counting WMOs ohm

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the command counter, the outputs of the second and third clock cycles of the synchronization unit are connected respectively to the first and second clock inputs of the control unit, the bits of the command counter bits are connected to the inputs of the first HR of the memory block, allowing the synchronization block input to be connected to the clock control output of the interval setting block, the meter bit outputs are connected to the second information input of the second memory block, the outputs of the register bits are connected to the third information input of the second memory block, the output of which is you ode device, and 40 control unit contains the elements And, trigger, command decoder and address decoder, the input of which and the input of the command decoder are connected to the command input of the control unit, 45 outputs of elements I. first to fourth are outputs of setting the initial state of the control unit, outputs elements And from the fifth to the eighth are the outputs of the write 50 of the control unit, the outputs of the elements And from the ninth to the twelfth are the outputs of the reading of the control unit, the output of the thirteenth element And is the output allowed I register 55 reading out the fourteenth AND gate is the output of the initial state of installation

the control unit, the output of the fifteenth element And is the output of the recording resolution of the control unit, the single output of the trigger is the enabling output of the control unit, the single input of the trigger is connected to the output of the sixteenth element And, the first clock input of the control unit is connected to the first inputs of the elements And from the first to the fourth and the ninth through the sixteenth, the first output of the command decoder is connected to the second inputs of the elements And from the first to the fourth and to the first inputs of the elements And from the fifth to the eighth, the second output of the decoder commands connected to the second inputs of the elements And the ninth to the thirteenth and the second input of the fifteenth element And, the third output of the command decoder is connected to the second input of the sixteenth element And, the fourth output connected to the second input of the fourteenth element And, zero trigger input is the second clock input of the control unit the first output of the address decoder is connected to the third inputs of the first and ninth And elements, the second output is connected to the third inputs of the second and tenth And elements, the third output is connected to the third input The third and eleventh And elements, the fourth output of the address decoder is connected to the third inputs of the fourth and twelfth elements, the fifth, sixth and seventh outputs. are connected respectively to the second inputs of the fifth, sixth and seventh ^- elements And, the eighth output being connected to the second input of the eighth AND gate and to the third input of the thirteenth AND gate, slot assignment unit comprises elements, NOR, NAND and counters, counting inputs of which are connected with the output of the corresponding elements And, the first inputs of which are connected to the synchronizing input of the interval setting block, the permissive input of which is connected to the second inputs of the elements And, the third input of each element And is connected to the output of the corresponding midrange This element is NOT connected to the input of the first NAND element, the output of which is connected to the first input of the second NAND element, the second input of which is connected

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with the enable input of the interval setting block, the installation and informational inputs of which are connected respectively to the installation and information inputs of the counters, the outputs 5 of which are connected to the enabling outputs of the interval specification block, the output of which is controlled by the outputs of the second AND-HE element. YU

FIG. 1 shows a block diagram of the proposed device; in fig. 2 · functional diagram of the sensor sampling unit; in fig. 3 - temporary di. the gram of signals generated by the synchronization unit 15; in fig; 4 is a functional block diagram of the control unit; in fig. 5 - ^ functional block of the interval setting block.

The device contains sensors 1, 20

Objects 2, sensor switching unit 3, multiplexer 4, memory unit 5, control unit 6, interval setting unit 7, AND elements 8, registers 9, counters 10, command counter 11, synchronization unit 25 12, memory unit 13, generator 14 clock pulses, groups of elements And 15, nodes 16 sampling of sensors, group of elements And 17, address selector 18, decoder 19, decoder 20 commands, address decoder 21, elements 22 - 37, trigger 38, counters 39 - 42, elements 43 46, the elements NOT 47 - 50, the elements AND-NOT 51 and 52.

The device works as follows.

Let us assume that the control object is co-located with a group of technological equipment with sensors 1 installed on it. Moreover, the sensors can be either frequency, or two-position and coded (parallel binary code). The device circuit is constructed in such a way that information from several sensors is simultaneously processed, i.e. The device is multichannel.

Next, we consider the operation of the device on the example of a four-channel version of its execution.

The logic of the device is to sequentially execute commands, encrypted in the form of multi-digit binary numbers and stored in memory block 5 (for example, reprogrammable block of permanent memory). .

The command format of memory block 5 contains four fields: A, B, C, ϋ. Field A is assigned to the first operation code (CPC 1) performed by the device at this time. Field B is assigned to the second operation code (COP 2) that is executed in the device during the operation of the command. Fields C and ϋ can be either an address part of a team or a part that stores data in digital form. Listing of fields A, B, C and ϋ is given in the table.

Field Number discharges Code operations The operation performed by the device one £ 3 four BUT one (COP 1) one The operation of the device in the mode of collecting and processing information sensors 0 The operation of the device in the automatic control mode AT 2 (COP 2)

00 Set counter 11 teams to zero

state

01 The interval 7 sensors with the corresponding addresses recorded in the C field are recorded with the number stored in the D field, or the register 9 with the corresponding addresses recorded also in the C field is recorded the information present at their first inputs

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Table continuation

I. 2 3

ten

Input of frequency signals in counters 10

C 3 001

010

From the counters 10 or registers 9 with the corresponding addresses recorded in the field C, information is copied into the memory cells of the second memory block 13, and the address of this cell is written in the ϋ field

The address of the first sensor intervals in block 7 and the first counter

The address of the second sensor intervals in block 7 and the second counter

011

100

101

110

¹¹¹

000

ϋ Any

The address of the third interval sensor in block 7 and the third counter

The address of the fourth interval sensor in block 7 and the fourth counter

Address of the first register in the group of registers 9

The address of the second register in the group of registers 9

The address of the third register in the group of registers 9

The address of the fourth register in the group of registers 9.

Addressing sensors or memory cells of memory block 13, data storage (settings of time intervals of block 7)

The addressing of the sensors in the device is as follows.

Input nodes 16 sample sensor fitted to equipment "po- ⁴⁵ means a ten-digit bus connected to a field ϋ unit 5, while providing addressing eto.m 1024 sensors. Let's say that each piece of equipment is not more than 32 datchi- Cove ^50, then it is possible to address up to 32 units of equipment. In this case, the five bits of the input bus are connected to the address selectors 18, and the other five bits are connected to the de- 5 encoders 19. The decoder 19 is a binary-decimal decoder that controls the output bus,

which, in turn, together with the element 15 connects to the input of multiplexer 4 (via a four-bit bus) one or another four of sensors 1. In addition, the address selector 18 generates a signal to allow the selection of sensors in a given piece of equipment when the code on its input matches the code assigned to this equipment.

Synchronization of the device is carried out using a generator 14 clock pulses and block 12 synchronization. Block 12 generates a sequence of clock signals (Fig. 2) TS1 ... TSZ, the purpose of which is the following: TS1 adds

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unit to the contents of the counter 11 teams; TS2 and TSZ synchronize the passage of commands in the device.

In addition, the generator 14 clock pulses forms two sequence. The reference frequencies are: £ _{? 1} , and £. _dt2 . £ _{E1I frequency} used

in the operation of block 7, and the frequency is used to simulate frequency sensors when the device operates in the auto-control mode.

The control unit 6 performs * decryption of the command recorded in this cell of block 5, and generates the output using the decoder 20 and 21, the elements 22 - 37 and the trigger 38 (Fig. 4) signals K1 ... K60, controlling those or other elements of the device. At the same time, the inputs of the decoder 20 commands are connected to the ²⁰ rows of cells of the .5 block allocated for the B field, and the inputs of the address decoder 21 are connected with the bits of the block 5 allocated for the C field.

In this example of building the control block 6, the signals K1 ... K4 arrive at the inputs of the corresponding counters 10 (set the counters to zero) and simultaneously control the operation of block 7.30. The signals K5 ... K8 arrive at the inputs of the corresponding registers 9 and provide record information in them. Signals K9 ... K12 arrive at the inputs of the corresponding counters 10 and provide for the reading of information from them. The signal K13 is fed to the control input of the registers 9 and provides for the reading of information from them. The signal K14 is fed to the input of block 7 and the inputs of the 40 elements And 8 and provides processing of frequency signals. The signal K15 is fed to the input of the counter 11 teams and ensures that it is set to the zero state. The signal K16 is fed to the 45 input of the memory block 13 and provides reception of information in its memory cells.

Unit 7 together with counters 1.0 forms a multichannel frequency-to-code conversion node in the device. 50 The main elements of this block (Fig, 5) are counters 39 - 42, operating in the subtraction mode and parallel recording of information.

Upon receipt of a sequence of 55 control signals from block 6 to

, chik 39 - 42 sequentially recorded binary numbers stored in

block 5 in the area of understanding я. Upon arrival of the signal K14 to the subtractive inputs of the counters 39-42, the frequency pulses £, _{γ 4} begin to flow through the elements E 43 46, with the result that the contents of the counters 39 - 42 decrease. In addition, the output element ·

AND-NOT 52 signal "Resolution" (RZR) takes the value of logical "0", resulting in (Fig. 3) stops the formation of a sequence of clock signals.

As soon as the contents of the counters 39 - 42 become equal to zero, the corresponding elements are AND 43 - 46 (are closed, thereby stopping the arrival of pulses £ _97ι1 at the subtracting inputs of the indicated counters, and the signals at the outputs 01 ... 04 accept the logical value "0". The elements NOT 47 - 50 and the elements AND-NOT 51 and 52 constitute a scheme fixing the moment when the contents of all counters 39-42 become equal to zero, and, if this condition is met, the signal at the output of the element AND-NOT 52 takes on a logical value " 1 ". Formation of a sequence of clock signals TS1 ... TSZ resumes.

Consider the various modes of operation of the device in the process.

Case 1. After passing the TC1 clock signal, the counter of 11 commands from block 5 selects the next command, for example, with the CPC code 2 equal to 01 and the code in the field C equal to 001 (the CPC code 1 value is indifferent in this case).

According to the clock signal, the TC2 signal, the operation is performed in accordance with the table, i.e. write to the counter 39 of the block 7 time interval and set the first counter 10 to the zero state. The next three teams then perform the same operations on the remaining three pairs of counters. Thus, the device is being prepared for polling frequency sensors.

The next fifth command after passing the next clock signal TC1 contains the codes: KOP 1 equal to 1, KOP 2 equal to 10, and the ϋ field - the code of the address of the four sensors (frequency) located on the test object. Until the next clock signal (TC2) arrives, block 3

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switching, selects the necessary four sensors and connects them via the communication channel to the inputs of multiplexer 4. Since the control input of multiplexer 4 is connected to the A field of the command of block 5 and the COP code 1 is 1 at this time, multiplexer 4 passes the sensor signals to the inputs corresponding elements and 8.

With the arrival of the TC2 clock signal, the control unit 6 generates, as described, the control signal K14 (the block trigger 38 is set to the state in which the output is a logical "1"), which opens a group of elements And 8 and elements X 43 · - 46 in block 7 The counters 10 begin to fill with the frequencies of the selected sensors, and the counters 39 begin with 42 of the reference frequency.

At the end of the time intervals, the signals 01 ... 04 of the block 7 'close the corresponding elements AND 8, and thus, in the counters 10, the values of the parameters measured by the corresponding frequency sensors are formed in the parallel code.

Then passes the clock signal TSZ, which removes the signal K14 (trigger 38 of block 7 is set to the state in which the output logic "0"). The next clock signal, TC1, prepares the device for the execution of the next command.

Consider the process of reading information from the counters 10 to the memory block 13 for storage and subsequent transfer thereof (if necessary) to the system at a higher level. This operation is necessary every time after receiving information from the next four sensors. For this purpose, a command is served with a KOP 2 code of 11. On this command, control unit 6, as described, generates control signals K9 and K16, as a result of which the information from the first counter 10 is read into memory block 13. To read information from four counters 10, it is obviously necessary to execute four such commands successively (differing only in codes In the fields C and ϋ).

Case 2. The next command selected from block 5 has the code KOP1 equal to 1, the code KOP2 - 01, and in

Field C recorded code 101. This is a mode of collecting information from two-position and coded sensors.

Switching unit 3 connects four sensors (or four digits of the encoder signal sensor code) in accordance with the code recorded in the C field of the command.

The multiplexer 4 is connected to the channel connecting its inputs with the switching unit 3 by means of the CPC 1 signal, and the control unit 6 generates the control signal K5, as a result of which information from the respective sensors is recorded in the first register 9.

The process of recording information in the next three registers 9 occurs when three more analogous commands are passed and the corresponding control signals are generated in Kb. . . K8.

The process of reading information occurs simultaneously from all four registers (i.e., the width of the read information is 16), similar to the first case and when the control unit 6 generates K13 ... K16 signals.

- Case 3, From block 5, a team is selected with a CPC 1 code equal to 0.

In this case, the inputs of the multiplexer 4 are connected to the generator output of 14 clock pulses, which forms the reference frequency £. Then at

the passage of commands in the sequence described in the first case, in certain cells of block 13, numbers are written according to which the higher level system can judge the functioning of the elements of the device that carry out the information conversion.

Case .4, From block 5, a command is selected with the COP code 2 equal to 00. In this case, regardless of the codes in other command fields, the K15 signal generated by the control unit 6, the command counter 11 is set to the zero state. This co-manda can be used if the number of sensors on the test object is less than 1024.

Thus, the introduction into the device of a multiplexer, an interval setting block, a group of registers, a command counter and a second memory block, as well as its construction according to the specified scheme, allows to reduce the number

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connections between the elements of the device located on the object of control, and the elements that collect and convert information from sensors. This, in turn, reduces the consumption of material (for example, coaxial cable) for organizing these connections. For example, to collect information from 1024 sensors in the proposed device, 14 communication lines are necessary, while in a known device 260 communication lines are necessary.

In addition, the proposed device has more functionality.

In contrast to the known device, it can interrogate both frequency and two-position and coded sensors, which makes 20

the device is more versatile. The possibilities of imitation of polling frequency sensors in the device increase the reliability of the entire object management system, since if this system contains data on the operation of the elements of the device for collecting and preprocessing information, it is possible (for a higher 10 level system) to exclude incorrect system actions on object management control.

There is a possibility of automatic control of individual elements of the device, which 15 extends its functionality and increases the reliability of the multilevel object management system with the means of collecting and preprocessing information at one of the levels.

Phage. one

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FIG. 2

FIE

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FIG. four

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FIG. five

Claims (1)

A DEVICE FOR COLLECTION AND PRIMARY INFORMATION PROCESSING, containing a sensor switching unit, whose information inputs are device information inputs, the first memory block, control unit, AND elements, the output of each of which is connected to the counter input of the corresponding counter, clock generator, the first output of which is connected with the information input of the synchronization unit, characterized in that, with the aim of expanding the functionality due to the implementation of polling frequency, two-position and coding these sensors and improve the reliability of work, it introduced the second memory block, interval setting block, command counter, registers and multiplexer, the information inputs of which are connected respectively to the information outputs of the sensor switching unit, the address input of the multiplexer is connected to the address output of the first memory block, the synchronization inputs of the multiplexer and the interval task block is connected to the second clock generator output, the multiplexer outputs are connected respectively to the information inputs of the registers and to the first inputs of the elements AND, the second inputs of which and the enabling input-In the interval setting block are connected to the enabling output of the control unit, the third inputs of the AND elements are connected respectively to the enabling outputs of the interval setting block, the information input of which is the first information input of the second the memory unit and the switching enable input of the switching unit are connected to the information output of the first memory block whose command output is connected to the control input of the control unit, output s · the initial state of which is connected to the installation inputs of counters, registers and command counter, the write input of the second memory block is connected to the write enable output of the control unit, the register write inputs are connected respectively to the write outputs of the control unit, the meter reading inputs are connected to the read outputs of the control unit , the output of the register read permission is connected to the register read inputs, the output of the first clock of the synchronization block is connected to the counting input of the command counter, in The outputs of the second and third clock cycles of the synchronization unit are connected respectively to the first and second clock inputs of the control unit, the bits of the command counter are connected to the inputs of the first memory block, the enable input of the synchronization block is connected to the clock control output of the interval setting block, the bits outputs of the counters are connected to the second information input 5TS., 1167599 the second memory block, the outputs of the bits of the registers are connected to the third information input of the second memory block, the output of which is the output of the device, and the control unit contains the elements AND, trigger, decoder command and address decoder, the input of which and the input of the command decoder control, the outputs of the elements And the first to the fourth are the outputs of the installation of the initial state of the control unit, the outputs of the elements And the fifth to the eighth are the outputs of the recording of the control unit, the outputs of the element And from the ninth to the twelfth are the readout outputs of the control unit, the output of the thirteenth element And is the output of register read resolution, the output of the fourteenth element And is the output of setting the initial state of the control unit, the output of the fifteenth element And is the output of recording resolution of the control unit, the single output of the trigger is enabling the output of the control unit, a single trigger input is connected to the output of the sixteenth element And, the first clock input of the control unit is connected to the first the inputs of the elements And from the first to the fourth and from the ninth to the sixteenth, the first output of the command decoder is connected to the second inputs of the elements And from the first to the fourth and to the first inputs of the elements of Is the fifth to the eighth, the second output of the decoder of commands is connected to the second inputs of the elements And from the ninth to the thirteenth and with the second input of the fifteenth element And, the third output of the command decoder is connected to the second input of the sixteenth element And, the fourth output is connected to the second input of the fourteenth element And, 1167599 the zero input of the trigger is the second clock input of the control unit, the first output of the address decoder is connected to the third inputs of the first and ninth And elements, the second output is connected to the third inputs of the second and tenth And elements, the third output is connected to the third inputs of the third and eleventh And elements, the fourth output the address decoder is connected ι to the third inputs of the fourth and twelfth elements And, the fifth, sixth and seventh outputs are connected respectively to the second inputs of the fifth, sixth and seventh elements And, the eighth in the stroke is connected to the second input of the eighth element AND, and to the third input of the thirteenth element AND, the interval setting block contains AND, NOT, AND-NOT elements and counters, the counting inputs of which are connected to the output of the corresponding AND elements, the first inputs of which are connected to the synchronizing input of the reference block intervals, the permissive input of which is connected to the second inputs of the AND elements, the third input of each element AND is connected to the output of the corresponding counter and to the input of the corresponding element NOT, the outputs of the elements are NOT connected, respectively to the inputs of the first NAND element, the output of which is connected to the first input of the second NAND element, the second input of which is connected to the enabling input of the interval setting block, the installation and information inputs of which are connected respectively to the installation and information inputs of the counters, the outputs of which are connected to permitting outputs of the interval setting block, the output of which the clock control is the output of the second NAND element. one