SU940164A1 - Device for distributing tasks for processors - Google Patents

Description

(54) DEVICE TO DISTRIBUTE JOBS TO PROCESSORS

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The invention relates to the launching of spesh and it can be used to automate the selection of a program from a set of information-related sets for a solution in a control multi-generation computing system.

A device for selecting tasks in a target data processing system is known, which contains a task index index, whose input is connected to a device input, a data register, AND, OR elements, a block for simulating arcs and graph vertices, prohibition elements, result registers, and a third-party memory node 1 3 Close to the present invention is a device for distributing tasks of the production process | containing a matrix of shapers for weights of arcs, each of which contains a trigger n. to the counter whose output is connected to the input TJHI of the ger, the output of the trigger of each column of the matrix of the forerunners of the scales of the arcs is connected to the corresponding, the input of the first element I, the clock pulse generator, the control unit comprising the second

, emeevrg And initial startup scheme, third element And, trigger, fourth element And, and-bit register of Attendants, register of selected vertices, At the fifth elements And, combination scheme, additional triggers by the number of columns of the matrix model, sixth elements AND 2 .

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A disadvantage of the known devices is low reliability.

The purpose of the invention is to increase the reliability.

This goal is achieved by the fact that

15 into the device for distributing the set processors containing the matrix model of the setp, bpsg control, the first output of which is connected to the control input of the encoder, the outputs of which are connected to the first inputs of the register of the encoder, and whose codes are the outputs of the device and connected to the first inputs elements of the first group, the second inputs of which are connected to the outputs of the register of selected vertices, whose inputs are the inputs of the device, outputs of the elements of the first group are connected to the inputs of the first groove triggers connected to the first output member and a second group, the outputs of which are connected with. information inputs of the encoder, the first group of counters and the third group of elements AND whose OUTPUTS are connected to mtJ codes (r / ErrVI 4V tT4 TT rfTfVrtf lff irr t rf .r - l ". counters of the first group, the outputs of which are connected to the second inputs of the elements g the second group, the second group of triggers, the second group of counters, the fourth group of elements AND and the group of elements whose inputs are connected respectively to the outputs of the matrix network model, the outputs of the elements OR NOT of the group are connected to the first inputs of the elements of the fourth group, the second inputs which are connected to the first inputs of elements AND of the third group and connected to the second output of the control unit, the outputs of elements AND of the fourth group are connected to the inputs of counters of the second group, the outputs of which are connected to the inputs of the matrix network model and the outputs of which are connected to the second inputs Elements of the group: and the group to the inputs of the control unit. The drawing shows a block diagram of a device for distributing tasks to processors. The device contains a matrix model 1 of the network consisting of triggers 2, according to the number of rows of the matrix, a group of elements OR NOT 3, according to the number of columns of the matrix, a fourth group of elements I 4, taken by a group of counters 5, a second group of triggers 6 8, the first group of flip-flops 9, the second group of elements and the Yu register 11 selected vertices, the priority register 12, the first ipyjuiy elements I 13, as well as the encoder 14, the generator 15 clock pulses, the first element And 16, the initial start circuit 17, the second element I 18, additional trigger p 19, the trigger input 20 of the device, data inputs 21 and an output device 22 of the device. The control unit 23 drives a generator 15, elements AND 16 and 18, the initial start circuit 17, trigger 19, input 20 to 21 Vi output 22. The device works as follows. Initially, information on the topology of the simulated graph is entered into model 1. In this case, the triggers (ij, 1; and), which are the formation of carcasses of arcs; They are installed in a single location, if there is an information link from the 1st vertex to the jth vertex. The corresponding trigger is determined by the intersection of - (- th row and - / th column. Other triggers 2.-;, as well as steps 6, 9 and 19, counters 8 are: - ... ... -4 s in the zero state. The counters of the 5 corresponding vertices of the graph bring in the number of pulses supplementing the weights of BejmmH to the total capacity of the counters. After entering the initial information on the inputs of the elements OR 3, combining the outputs of the flip-flops 2 in the coc-i-corresponding final vertices of the graph, high potentials. This is due to the fact that in a unidirectional graph without cycles and loops, The vertices do not contain outgoing branches, and therefore all the triggers 2 in this line will be in the zero state, initially the device determines the maximum paths from this vertex to the final vertex of the graph describing the set of information-related problems. By the start signal at the input 20 of the initial start circuit 17, the pulses from the generator 15 output go to the inputs of elements 4 and 7, and then to all counters 8, since in the initial state all the triggers 6 are in the zero state andmye inputs of AND gates 7 are connected to the zero outputs of flip-flops 6. Furthermore, counting pulses are fed through the elements 4 and 5 on those counters for which trsh Gery 2 homonymous rows of the matrix are in the zero state. Therefore, a high potential appears at the output of the corresponding elements OR-HE 3, so that at the controlled input of the element of the same name AND 4 there will be a high potential. By counting the number of pulses, nponof is donal to the weight of the modifiable vertex, counter 5 overflows, sets the corresponding trigger 6 to one state, and all triggers 2 in this column of the matrix model are in the zero state. The flip-flop of the trigger 6 into a single state ensures that the ampli- fication of the counting pulses through the element 7 to the input of the registering counter 8, which contains the code of the maximum path from the given vertex to the final verse of the graph of the information-related set of problems. The computational process continues until the low potentials are present at the outputs of all the flip-flops 6. At the output of the element OR 18 there will be a low potential, as a result of which the supply of counting impulses from the output of the generator 15 through the element 16 coincides with the information inputs of the AND 4 and 7 elements. From the output of the trigger 19, a high potential is also supplied to the controlled input of PDR 14, which provides a high potential on one or several of its outputs, which correspond to the maximum code stored on the eight counters of the same name 8. To the input of the encoder 14, codes from counters 8 are fed through elements 10, to the controlled inputs to toryh high potential is supplied to the zero outputs of flip-flops 9. As a result, the code register 12 is set comprising a set of zeros and odvoa or more units. This code is fed through the output busses 22 to the supervisor of the computing system (not shown), which selects the next program for implementation, for which the corresponding register register bit 12 is one. If there are several units in the register 12 at the same time, the supervisor selects the next program, for which is the smallest bit number that contains the unit. After selecting one of the program sets for implementation in the computer system, the supervisor writes the corresponding number (for example, L 1; and the selected program p The register register 11 is 1. As a result, element 13i has a high potential at the output, by which trigger 9 and goes into one state, the flow of code from counter Si to inputs of encoder 14 is also stopped in register 12 and recorded with another code, to which the supervisor selects unimplemented programs. The device stops working when a zero code appears on register 12. Thus, the proposed device, by introducing new elements with appropriate connections, ensures the distribution of a set of information associated with ach the processors of the computing system suschestve1sho sokraschayuts hardware costs (priblizitep- DK, with an accuracy of one trigger on (and -) counter to which a skid number of pulses are for supplementing the weight peaks to the total counter capacity) compared with the known. Reducing hardware costs in a device that performs the same functions leads to a corresponding increase in device reliability. Formula of the Invention A device for distributing tasks to processors containing a matrix network model, a control unit, the first output of which is connected to the control input of the encoder, the outputs of which are are connected to the inputs of the priority repaogram, whose outputs are the outputs of the ycJV relay and connected to the first inputs of the AND elements of the first group, the second inputs of which are connected to the register slots selected vertices whose inputs are entrances of the device, the outputs of the elements And the first group are connected to the inputs of the trigger of the first group, the outputs of which are connected to the first inputs of the elements And the second group, the outputs of which are connected to the information inputs of the encoder, the first group of counters and the yarn group of elements I, the outputs of which are connected to the inputs of the counters of the first group, the outputs of which are connected to the second inputs of the elements of the second group, distinguished by the fact that, in order to increase the reliability of the device, the second g Upp Triggers, the second group of counters, the fourth group of elements AND, and the group of elements OR NOT, whose inputs are connected respectively from the output of the high-voltage network model, the outputs of the elements OR NOT NOT connected to the first inputs of the elements AND the fourth group, the second inputs of which connected to the first inputs of the elements And the third group. They are connected to the inputs of the second group, the outputs of which are connected to the inputs of the matrix model of the network and the inputs of the second group trigger, the outputs of which are connected to the second inputs of the elements of the third group and to the inputs control unit. Sources of information taken into account in the examination 1. Author's certificate) No. 664175, cl. Q06F 15/20, 1976 .. 2. USSR author's certificate in accordance with Me 2886510/18-24, CLP.OOR 15/20, 1979 (prototsch)

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Claims (1)

Formula of the invention A device for distributing tasks to processors containing a matrix model of a network, a control unit, the first output of which is connected to the control input of the encoder, the outputs of which are connected to the inputs of the priority register, the outputs of which are the outputs of the device and connected to the first inputs of the elements And the first group, the second inputs of which are connected to the outputs of the register of selected verps, the inputs of which are the inputs of the device, the outputs of the elements of the first group are connected to the inputs of the triggers of the first group the outputs of which are connected to the first inputs of the AND elements of the second troupe, the outputs of which are connected to the information inputs of the encoder, the first group of counters and the third group of AND elements, the outputs of which are connected to the inputs of the counters of the first group, the outputs of which are connected to the second inputs of the AND elements of the second group, characterized in order to increase the reliability of the device, a second group of triggers, a second group of counters, a fourth group of AND elements and a group of OR-HE elements, the inputs of which are connected respectively to odes matrix network model outputs OR-HE element group are connected to first inputs of AND gates of the fourth group, the second input being connected to the first inputs of AND gates third grup-. are connected to the second output of the control unit, the output of AND elements of the fourth group are connected to the inputs of the counters of the second group, the outputs of which are connected to the inputs of the matrix model of the network and to the inputs of the triggers of the second group, the outputs of which are connected to the second inputs of the elements of the third group and to the inputs of the block management.