SU212628A1 - PREFERENCE TO DIGITAL COMPUTER MACHINES - Google Patents

Description

The well-known auxiliary units to digital computers make it possible to somewhat reduce the main machine time when solving a number of statistical problems.

The proposed device allows one to obtain a significantly greater gain in counting time, since it is a specialized digital machine, including a random binary number generator, a control device, a device for checking logical conditions, a memory block, a buffer and an arithmetic unit.

The drawing shows a block diagram of the proposed set-top box, where the following is taken, its designation:

/ - randomly distributed pulse generators;

2, 3, 4 - replaceable random pulse generators with fixed distribution laws;

5- logic converter;

6- register;

7- switch;

8- multi-digit adder;

9- valve circuit;

10- resolution block; 11, 12, 13 - counters;

16- set of valves;

17- adder arithmetic unit; positions g, 226, 27, 28 are designated

interconnect between blocks. B l to I.

A controlled generator of random variables GSH to obtain a random code with a probability distribution depending on the control input of the GSH on each tick of the prefix of the random code. Blocks 1 are standard generators of random standardized pulses that at each moment emit a zero or one with a probability of 1/2. Blocks 2, 3, and 4 are interchangeable random pulse generators with fixed distribution laws. Unit 4 may be required to simulate the Novo-US process, in particular, when simulating queuing systems. Blocks 2, 3, 4 are identical to blocks). Block 5 is a logic converter with four random inputs, twenty four control inputs and six random outputs. The values of the control inputs are determined by

register 6.

The control input of block 5 (or register 6} is divided into groups as follows: Register 6 also has control input 24 with values of "O or" 1. Depending on the setup program, the contents of the register or does not change during the simulation after filling in the paste-in moment, when the input 15 is blocked, the input 15 is not blocked, and then the input 7 determines the start and stop of the random variable generator Block II. A conventional converter serves to convert the random code into a random value with a local distribution of ver It is a switch 7, a twelve-bit adder 3 with a transfer device that provides blanking of the transfer unit from any three bits of the adder defined by the setup program, and the valve circuit 9. The input / delivery to unit II is a combination of the type 000100, which is interpreted by switch 7 as follows: one at an even place — add, one at an odd place — subtract (add in the return code) one digit of the adder one if it occurs in the first pair of the input code, respectively th discharge for the second and the third pair of discharge for the third pair (e.g., a combination of both 000100 istolkovyvaets add "1 in the second discharge). Inputs 2, 3 and 4 deliver to block II on each tick "O or" 1, which, depending on the values of the constants of the tuning program, are either blocked or added by the switch 7 to the above digits of the adder, or the operation is determined by adding The unit was received or subtracted to the corresponding bit, arriving at the controlled input G (and only one of the inputs worked - the corresponding controlled input that worked in this cycle). Input 10 serves to store in the adder an initial value stored in a specific cell of a memory unit, for example, "01. Input 24 serves to adjust the conditional converter at the beginning of operation. Input 8 is control - it reads the value of the adder at output 5 at some stops of the console. Output 6 is the main one — through this output, the contents of the adder go to memory block III and, according to the address, the information from a certain cell is selected. The output 5 is used to transmit to the buffer device of the CU (block VI) the contents of the adder 8 according to the signal of the control device (input 8). Block III. This is a memory block that serves to encode the initial state of the system and the control and computational parts of the simulation circuit. Block 14 is a switch that connects the key input of block I with a group of bits of a memory cell allocated for encoding a probability distribution. Block 15 is the actual standard cube of memory in 4,096 cells of 45 binary bits each. According to the setup program, part of the storage capacity of 1, 64, 256 and 1024 cells is allocated for the buffer memory and is used to record information from the buffer and arithmetic devices. Z1 P.2 Pz P Pg, Yao - means the probability distribution code, which will be simulated by the generator of block I in the next test step. Depending on the conditions of the problem, this code may occupy a maximum of 24 bits (6X4). A zero code, for example, is perceived by the prefix as a signal that block I is constantly working with the same distribution defined by the contents of the memory cell, for example, "00, Input 6 receives the address of the cell from which information will be read a read enable signal from block IV on input 9. Input 25 is used to write information to the memory from the buffer device (block VI). Input 19 is used to record information in the memory of the arithmetic unit (block V). The output 16 is used to write to the adder 8 an initial value stored in the " 01 memory block " cell. The output 17 is used for reading into the buffer device and in the computer the contents of a number of memory cells. The group of inputs //, 12, 14, 15 transfers to the destination the contents of the cell where the read occurred, if it took place. Block IV. The control unit serves to organize the operation of the console in the main modes. Block 10 is an enable block that distributes permission signals to the operation of prefix blocks depending on their input signals. Blocks 11, 12, 13 are counters that determine the cyclical operation of the console. The counter 11 at a single signal in one of the bits of the tuning program is filled at input 14 when read from the memory in the operating mode, and at zero signal it is filled at input 3 with a random code. Counter 12, when there is a unit in the second bit of the setup code, is filled at input 13 each time the arithmetic unit responds to pulses, the number of which is given by the contents of cell 10 memory, and if there is a signal, it is filled once code at input 4. Counter 13 provides one operation for a specified number of operations of the arithmetic unit. This number is constant and taken to be 4096 (a twelve-bit counter). With the presence of "1 in the third bit of the code of the setup program, the counter 13 does not skip all the operations of the arithmetic unit (block V), in the presence of" O - only individual operations. At input 22 in block IV, an arming signal is triggered, and input

bets either at the start of operation or after stopping the set-top box with the transfer of control to the buffer device. Output T generates block start signals / continuously if there was a start signal for the device and no stop signal for any reason. The reasons for the shutdown may be the operation of blocks III, V and VI. Output 8 generates a signal to transfer the contents of the adder unit II. block VI, which appears after each stop of block I. On output 9, the enable signals are triggered by the block (read permission). Such a signal appears when a counter is triggered // for comparison, that is, when the number of alarms triggered is equal to the value of counter 11. Output 10 gives permission to trigger a block V. Such a signal appears when the counter 12 is triggered.

Block V.

The arithmetic unit (LU) is used to sum the contents of the memory cells, transfer the contents of the accumulator to the buffer device and to group the contents of the group of memory cells grouped depending on the operation code defined by the setup program. Block 16 is a valve device, a P-adder unit of an arithmetic unit. At input 18, block V receives the functional part of the contents of the selected memory location. Input 10 receives permission from block IV to perform the operation. Input 22 enters V in the setup program, namely the operation code and switch setup code 14. Output 19 sends the result of the operation to the main part of the memory — to the same cell, the contents of which were processed. Output 20 transmits the result to a buffer device — for writing to the buffer portion of the memory. Output 21 transmits the functional part of the contents of the cell directly to the buffer device without processing in L U. Output 22 sends a signal that the operation in the DR has been completed. The opcode values may be as follows;

A - block I does not process the processing - the functional part of the contents of each selected cell with the permission "1 is transmitted to the buffer device;

B - the functional part of the contents of each selected memory cell at a resolution of "1 is added to the contents of the next in order cell of the buffer memory (starting from the first cell). This process goes on until the buffer memory is full, when the resolution of 2 appears, and the process begins again from the first cell of the buffer memory. If resolution “3” appeared (it could appear only earlier than resolution “2), then the content of the last selected cell is added to all other cells that have not yet participated in the process of adding the buffer memory to the beginning.

Noah memory cell is summed in the LU adder of the block V. By resolution "4" the contents of the adder are output to the buffer device; G - for each resolution "2 or 3

function. The part of the contents of the selected memory cell is added to the unit and the result is written back to the same cell. The blocking of the V block with the transfer of the Control to the buffer device is terminated

in L mode by resolution “2 or“ 3, in modes B, C and D by resolution “4. Block VI.

The buffer device serves to connect the console with EVL1 control in recording modes

and reading information, setting up prefix blocks based on the setup program coming from the computer, controlling the start and continuation of the console. The inputs 21 and 22 receive the processing result from

block V, the input 17 reads the contents of the memory, the input 5 receives the value of the adder of the block II, the input 27 receives information from the computer, the input 28 receives the control information

from block IV. The output 23 serves to start up the set-top box, the output 24 spreads the set-top box setup program to the corresponding blocks, the output 25 provides for recording information in the set-top box, the output 26 for transmitting control and numerical information to the computer. The buffer device operates in four modes:

1) recording information from a computer into the memory of the device;

2) enter the setup program;

3) recording the current solution information in the buffer part of the memory;

4) reading information in the computer from the prefix memory.

In the L, B and C modes of the arithmetic unit, the information entering the buffer unit is immediately rewritten into the buffer part of the memory. In G mode, the buffer device is not involved. In mode L with a resolution of "2 or" 3, the buffer device transmits a recall command to the computer.

Depending on the V block and the setup program, the resulting trajectory of the random process is processed. AT

The buffer part of the memory accumulates either the trajectory itself or the value system of the function on it (mode L), or the average of some chain function simultaneously for all points of the simulated process interval (B}, or the average of some random variable defined by the chain (mode B. In mode D the absolute probability distribution of the states of the circuit being simulated at a certain step, which accumulates directly in the cells encoding the states of the circuit, is calculated.

In mode B, for example, the following tasks are solved; calculating certain integers for a partial differential equation of the 2nd order of an elliptic type of a general form; boundary value problem for heat conduction equation; modeling the passage of a particle through a layer of matter; simulation of queuing systems; solution of systems of nonlinear equations of large order. In A mode, it is possible to obtain solutions of systems of linear algebraic equations of high order and the value of continual integrals; processing in the computer the trajectories of the functions of Markov chains, issued by the device, to model the processes of resource allocation during production and construction; simulate a chain reaction. In mode B, the boundary problem for the equation of heat conduction is very effectively solved, and in mode D it is possible to predict the evolution of production and economic systems from the point of view of the distribution of material resources at a certain stage of time.

Subject invention

A prefix to digital computers for solving statistical problems, containing random binary number generators with uniform distribution, registers, memory block, decoders, valves, a buffer device, a control device, and a conditional converter, in order to improve speed

modeling arbitrary homogeneous Markov chains of high order in multiprogram operation mode, part of random number generators depending on the program

directly, and the other part through a controlled code converter and through a controlled switch is connected to a controlled composite adder, the output of which through a valve is connected to the input of a buffer

devices connected by outputs through a controlled switch with a code converter of a random number generator, with an arithmetic device, with comparison meters of a control device and with a buffer device, the outputs of the arithmetic device being connected to a memory unit, a buffer device, with a control device decoder, and outputs a buffer device connected to a device decoder

control, to the register of the random number generator, to the switch and the composite adder of the conventional converter, to the switch of the memory block and the arithmetic unit, to the autonomous control system of the usb block and directly to the external input of the digital computer, the outputs of the registers are associated with the decoder of the control unit The outputs of which are connected to a random binary number generator, to the valves of the conditional converter, to the memory block control system and to the arithmetic unit adder. oystva.

r i:

27