SU1157505A2 - Device for non-linear processing of electric prospecting signals - Google Patents

Abstract

DEVICE FOR NONLINEAR TREATMENT OF ELECTRIC SURVEY SIGNALS by author. St. No. 1073728, characterized in that, in order to improve the accuracy of the evaluation of the measured parameters, a sign register, a buffer register, a division block, a counter, a second comparison circuit, a character matching circuit and an AND element are entered into it, the first and second inputs of the second comparison circuit connected to the information inputs of the arithmetic unit, the code of the second comparison circuit is connected to the input of the character matching circuit and the input of the register of the mark whose output is connected to the input of the buffer register, and the output of the buffer register connected to the second input c we match the characters, the control input of the buffer register is connected to the control input of the arithmetic unit, the first and second control inputs of the sign register are connected respectively to the control inputs of the arithmetic unit and the second (L register, the counter input is connected to the service output of the input unit, three inputs the element And are connected respectively to the output of the counter, the output of the circuit of matching characters and the control input of the arithmetic unit, and the output of the element And is connected to the control input of the block e l In the division, the information input of which is connected to the output of the arithmetic unit, and the output - to the inputs of the second register and the first comparison circuit.

Description

The invention relates to experimental geoelectromagnetic devices and can be applied to. measurements of noisy, repetitive signals in the method of sound polarization (VP) and the method of transient processes (MGS). According to the main auth. No. 1073728, a device for nonlinear processing of electrical prospecting signals is known, comprising an input unit, first and second registers, a comparison circuit, an arithmetic unit, a memory device, a control unit and two switches, and the information output of the input unit is connected to the memory input, and the service output of the the unit is connected to the input of the control unit, the output of the storage device is connected to the first input of the arithmetic unit and through the first switch to the input of the first register a, the output of the first register is connected to the input of the arithmetic unit, the output of which is connected to the input of the second register and the first input of the comparison circuit, the output of the second register is connected to the second input of the comparison circuit and through the first switch to the input of the first register and the output of the second register the switch is connected to the output of the entire device, the output of the comparison circuit is connected to the second input of the control device, the outputs of the control device are connected to the control inputs of the first and second registers of the memory Triplets, arithmetic units and switches. The disadvantage of this device is the relatively low convergence rate of target parameter estimates to the true value under conditions of characteristic noise in geoelectroscopic conditions, which are a mixture of small fluctuation and rare (anomalous) impulse noise of large amplitude. The drawback of the device is due to the fact that if you exclude the most distant from the evaluation of samples, only a small amount of interference can eliminate the sample on several periods of the signal that have the same difference signs with the current estimates of the measured values, which sometimes leads to a shift in the estimates. The purpose of the invention is to improve the accuracy of the evaluation of the measured parameters. The goal is achieved by the fact that the sign register, the buffer register, the division block, the counter, the second comparison circuit, the character matching circuit and the terminal I are entered into the device for nonlinear processing of electrical signals, the first and second inputs of the second comparison circuit being connected to the information inputs an arithmetic unit, the output of the second comparison circuit is connected to the input of the character matching circuit and the register of the sign, the output of which is connected to the input of the buffer register, and the output of the buffer register is connected to the second By the input of the character matching circuit, the control input of the buffer register is connected to the control input of the arithmetic unit, the first and second control inputs of the sign register are connected respectively to the control inputs of the arithmetic unit and the second register, the counter input is connected to the service output of the input unit, three inputs element And are connected respectively to the output of the counter, the output of the coincidence circuit of characters and the control input of the arithmetic unit, and the output of the element AND is connected to the control input of the block division, whose information input is connected to the output of the arithmetic unit, and the output to the inputs of the second register and the first comparison circuit. In the drawing, a block diagram of the device is shown. The device for nonlinear processing of electrical prospecting signals comprises an input unit I, a storage device 2, a first switch 3, a first register 4, a counter 5, a control device 6, a second comparison circuit 7, an arithmetic unit 8, a character register 9, AND element, dividing unit I , a character matching circuit 12, a second pivot 13, a first comparison circuit 1A, a second switch 15 and a buffer register 16. The information output of the input unit 1 is connected to the input of the storage device 2. The service output of the input unit 1 is connected to the input of the devices and 6 controls. Memory output 2

connected to the first inputs of the second comparison circuit 7 and the arithmetic unit 8, as well as through the first switch 3 to the input of the first register 4. The output of the first register 4 is connected to the second inputs of the second comparison circuit 7 and the arithmetic unit 8, the output of the arithmetic unit-8 is connected to the input of the division unit 11, the output of which is connected to the input of the second register 13 and the first input of the first circuit 14, as compared. The output of the second register 13 is connected to the second input of the first comparison circuit 14 and through the first switch 3 to the input of the first register 4. The output of the second register 13 is also connected to the output of the entire device through the second switch 15. The input of the counter 5 is connected to the service output of the input unit 1, and its output is connected to the first input of the element AND 1

The output of the second circuit 7 comparing yen with the information input of the register of the sign 9 and with the first input of the circuit 12 matches the characters. The output of the register of sign 9 is connected to the input of the buffer register 16. The control input of the buffer register 16 is connected to the control input of the arithmetic unit 8. The second input of the character matching circuit 12 is connected to the output of the buffer register 16, and its output is connected to the second input of AND 10 The third input element And 10 is connected to the control input of the arithmetic unit 8. The first and second control inputs of the register of the sign 9 are connected to the control inputs of the arithmetic unit 8 and the second register 13. The outputs of the control unit 6 with dineny with the control inputs of the first 4 and second registers 13, memory device 2, the arithmetic unit 8, and switches 3 and 15.

The division unit 11 is designed to perform a division operation by a predetermined coefficient, and in the absence of a signal at its control input, transmits the code pattern from the output to the output unchanged.

Counter 5 is intended to allocate periods with a number greater than N + 1.

The register of the sign 9 serves to memorize the sign of the difference between the readings and can be made on the basis of the LC trigger.

The device works as follows.

The input unit 1 samples and converts the input periodic signal to a code and determines one or several target parameters (one or several points on the transient response, amplitude or phase parameters} during one period.) Each of the target parameters is treated the same way, therefore the following description work to simplify is done for one parameter.

Upon completion of the conversion, a signal is generated at the service output of the input unit 1, according to which the control device 6 generates the write command and the cell address of the memory 2. After passing N periods and recording 2 samples in the memory, the device determines the median of sums x + x, where; and j can take any values from I to N,

Dp of determining the median, the control device 6, after writing to the storage device 2N of samples, generates a signal permitting the recording of the first reference stored in memory 2 to the first register 4. Thereafter, the control device 6 begins a sequential poll of all N samples

Commands stored in memory 2 in arithmetic unit 8 determine the sums of incoming samples and samples stored in the first register 4. The first sum x + Xg is written through the divider without changes to the second register 13, and from the output of the second register 13 enters to the second input of the first comparison circuit 14. The second sum X + x goes to the nepBbdt input of the first comparison circuit 14, and if the second sum is greater than the first, the control unit 6 allows the recording in the second register 13 of the new sum to be output from the output of the first comparison circuit 14. If the second sum is less than the first, then in the second register 13 there remains the first sum until the first input of the first comparison circuit 14 comes up with an amount larger in magnitude than that recorded in the second register 13. After iterating through all N samples stored in the storage device 2, in the second register 13, is the largest of the sums generated with the first reading, i.e. max x + + X., and a second count is recorded in the first register 4 and the enumeration is repeated. After completing N + 1 searches, the largest member of the variation series will be found. The address code of the items is stored in the control unit 6 and when determining the previous members of the variation series, the sum formed by these items is not calculated. The previous members of the variational series are determined similarly. After determining (N + 1) + 2 members of the series, further determination is stopped, and the signal that unlocks the second switch 15 and the contents of the second register 13 (i.e. The middle term of the variational series I arrives at the output of the device (the result can be divided by 2 except the least significant bit), the estimate of the value of the measured parameter 0 is determined in the interval between the arrival of N-ro and H samples. N from the accounts determined An and recorded in a 2N + .l st readout memory, an operation is performed on the determination and deletion of the readout 2 of the counting that is the most different from the 9th estimate. To do this, in the first register 4, by command from the output of the control device 6 through the first switch 3 is recorded from the output of the second editor 13 containing a score of 0 there. At the same time, from the output of control device 6, a signal is received to change the operation performed by the arithmetic device 8. After the arrival of this signal, the arithmetic device 8 performs The operation of code I § - X; I, i.e. finds the modulus of the difference between the samples arriving at its inputs. The same signal is fed to the first control input of the register 9 characters and allows writing to the register 9 characters when a signal arrives at its second control input. The control unit 6 performs a sequential polling of 2 N + 1 samples stored in the memory. The difference module 0, obtained at the output of the arithmetic unit 8, is transmitted by dividing unit 11 without changes and is recorded in the second register 13. At the same time, the sign of the difference d x, obtained at the output of the second comparison circuit 7, is written to the sign register 9. 1 l. The difference module stored in the second register 13 is compared with the difference module between the estimate § and the second sample X2. If I is 0., - Xj I is greater than the difference 8 -, the first comparison circuit 14 produces a signal allowing writing the second register 13 to the value 1 21 and also to the register 9 the sign of the difference sign 6, - Xd, If the modulus of the difference I b is X2 I less | ё., - х | then in the second register 13 the first difference modulus remains, and in the sign register the former difference sign remains until the output of the arithmetic unit 8 receives a number exceeding | b - x. After iterating through the N4-1 counts stored in memory 2, the second register 1 3 has the largest difference modulus, in register 9 the sign is the sign of this difference, and in control device 6 the code of the reference address most deviating from according to the first N count estimates 9, This count is erased from the memory 2, i.e. in memory 2, cells are made available for recording the N + .2 count. The falling edge of the signal switching the operation mode of the arithmetic unit 8 records the sign of the difference stored in register 9, into the buffer register 16. Thus, the sign of difference between the excluded reading and the estimate obtained in the previous period is stored in the buffer register 16. From the remaining readings, the second estimate of S is determined, i.e. for the remaining N samples, the operation of determining the median of the row composed of half sums is repeated. After the second estimate b has been determined and N + 2 counts are recorded in memory 2, an exception is made from the storage device 2 that is the most different from the estimate e. Preference is given to counts with the difference sign with estimate b, reverse compared with the sign of the difference between the excluded in the previous period, the counting and evaluation. To do this, in the first register 4, at the command from the output of the control unit 6, through the first switch 3 is recorded the output of the second register 13, containing the evaluation § there. Simultaneously, from the output of control unit 6, a signal is received to change the operation performed by the arithmetic unit 8. After the input block IN has received the 2nd estimate, the output of counter 5 sets a signal to enable element 10. The control unit 6 performs a sequential poll. vshhs in the storage device 21 + 1 samples. The difference sign 02 -1 obtained at the output of the second comparison circuit 7, goes to the first input of the character matching circuit 12, and the second input receives the difference sign stored in the buffer register 16. If these characters match, the output from the output of circuit 12 matches the characters through element And 10 is fed to the control input of the block D division. In this case, the division unit I1 divides the code corresponding to the modulus of difference b x) by a given coefficient K. If the characters at the input of the circuit 12 do not match the characters, the Equipments block transmits the modulus of difference (02-х) to its output without changing . The code combination received at the output of dividing block 11 is transferred to the second register 13, and the difference sign is written to the register of 9 characters. It then determines the sign of the difference j - x. and is compared with the sign stored in the buffer register 16. If the sign of the difference Sj - Xj and the sign of the difference between the 9 samples excluded in the previous period coincide, then the modulus of the difference j 02 2 obtained at the output of the arithmetic unit 8, shares with the block 11 dividing by the coefficient otherwise the modulus of the difference I p I (2 x, I is transmitted to the input of the second register 13 and the input of the first comparison circuit 14 without change. If the value is I J J-X 21 is greater than jj x J v K, and K take the value of either 1 or K depending on the result of the comparison of characters, corresponding to , And 2 x 1 ° with sign E1IMSYA stored in the buffer register 16), the first comparison circuit 14 vyrabatsha a signal recording during the resolving 1 second register 13znacheni t: r b x I K 1, K l "1; Z If I led gchina gg- 9, less 1L) 1 1 l I yy-- 9, - X, then in the second register KT I -i 1 I J 13 remains; p I b - those. 1 pore from the output of the division block. 11 will not receive a number greater than 1 1 I g - 0, - X. L After iterating through the N + 1 1 count stored in memory 2, in the second register 13 the largest of the 1 A I - 02 Xjl I i values is equal to a given coefficient K, if the difference sign is Xil coincides with the sign of the difference between the estimate in. and counting excluded in the previous period, otherwise K 1. In the register of the 9th sign there is a sign of the counting that forms the largest of II / I values - I 9, - X. I, and in the control unit 6, the address code of this reference. This count is erased from memory 2, and the remaining N counts determine the next estimate 9j. Further, the device operates as described above. The device was tested when working with K coefficients equal to 1.5; 2; 3 and 4, the best result was obtained with K2. To test the proposed device, an interference was applied to its input with a zero input signal having the following distribution density: - 2 -Iir vjiTr -TIT where t is the probability of the appearance of a pulse interference having a variance of 6; 6 is the dispersion of the fluctuation disturbance, and 6 "(. This disturbance is characteristic of geoelectromagnetic exploration, where with probability (l -eiE" 1 the signal is distorted by small fluctuation disturbances distributed according to the normal law with dispersion 6i but sometimes with probability ft acts impulsively interference with dispersion 6 |. The test is performed for a device having N + 1 .6 memory cells 0510 with a total number of samples equal to 7. When tested, the known device was compared with the proposed one and with averaging for different f and 6, with 0.0, Results calculated The standard deviation (RMS) of the estimation error for averaging and evaluating the device known and proposed is given in the table.

The table shows that the predla; The device allows you to get a gain for large and accurate compared to the known one by about 1.5 times, or a gain of 10 times as compared to averaging.

 The win by accuracy with a fixed number of repeated measurements or the gain by the number of repeated measurements at a fixed accuracy is achieved by introducing the weighting of excluded counts taking into account the sign of the excluded count.

Claims (1)

DEVICE FOR NONLINEAR PROCESSING OF ELECTRIC EXPLORATION SIGNALS by ed. St. No. 1Q73728, which is characterized in that, in order to increase the accuracy of the assessment of the measured parameters, a sign register, a buffer register, a division block, a counter, a second comparison circuit, a coincidence circuit of characters and an And element are introduced into it, the first and second inputs the second comparison circuit is connected to the information inputs of the arithmetic device, the output of the second comparison circuit is connected to the input of the sign matching circuit and the input of the sign register, the output of which is connected to the input of the buffer register, and the output of the buffer register is connected to the second input of the circuit with coincidence of characters, the control input of the buffer register is connected to the control input of the arithmetic device, the first and second control inputs of the sign register are connected respectively to the control inputs of the arithmetic device and the second register, the input of the counter is connected to the service output of the input unit, the three inputs of the element And are connected respectively to the output of the counter , the output of the sign matching circuit and the control input of the arithmetic device, and the output of the And element • is connected to the control input of the division unit, Discount input of which is connected to the output of the arithmetic unit and output - with the second register and the first inputs of the comparator circuit. SU P 57505 1 1,157,505 2