SU1146781A1 - Device for controlling rectifier converter - Google Patents

Abstract

1.USTROYSTVO CONTROL rectifier converter, containing a present master oscillator clock pulses, the microprocessor vychisyitelny unit comprising a microprocessor with two inputs prershani, pragrammno-defining block, two parallel input and parallel output information block, the block distribution otpirayup1ih pulses whose outputs are intended to be connected to the control electrodes of the converter valves, and the inputs are connected to the outputs of the first information output unit, the zero-organs block and the register a phase polarizer of three-phase mains, the inputs of which are connected to the power supply ceTij, containing six-bit information and pulse outputs, distinguished by the fact that, with the aim of expanding the functionality of the device by reducing the computer time spent by the microprocessor to control the valve unlocking angle, it is equipped with a block of clock counters with a clock input, a pulse, an output, two information and one control inputs, a block of null-organs and a registrar pol rn The phases are equipped with a control input, nprf than the six-bit information output of the zero-organ unit and the phase polarity recorder is connected to the information input of the information input unit, the control output of which is connected to the control input of the zero-organ unit and the phase polarity recorder, the pulse output of which ( O is connected via the information input unit to the first microprocessor interrupt VCOG1U to start the interrupt service routine from the "ynj-ops", information and control outputs of the second output unit in Loomings are connected respectively to the first and second information and control inputs of the meter block, O) the clocking input of which is connected, to the output of the master clock generator, and the pulse output to the second interrupt input of the microprocessor to start the clock pulse interrupt routine. 2. The device according to claim 1, characterized in that the block of zero-organs and the phase polarity recorder contains six channels for converting information about the state of the phase polarities of the three-phase supply network with a series-connected

Description

null-organ and driver of synchronization pulses in each of the channels, an isolation transformer, the primary phase windings of which are connected in a triangle and connected to the Y-circuit, and the secondary connected to a star and connected to the corresponding pairs of zero-organs, one for positive and one for for negative values of the corresponding linear supply voltage in each pair, controlled six-bit register on six 2I elements with six-bit information input and output and control input 1 to six-bit: a BI-NOT element, with the zero-output outputs connected to the six-input information input of the control register, the output of which is connected to the information output of the blocks, the control input of which is connected to the control input of the register, and the outputs of the zero-organs through the corresponding pulse formers synchronization associated with

the inputs of the element 6I-NOT, the output of which is connected to the pulse output of the block.

3. A device as claimed in Claims 1 and 2, characterized in that the clock counter block contains two non-reverse deducting counter counters of the anodic and cathodic groups of the bridge valve converter, respectively, a counter control unit and a counter priority determining unit, the clock input of the block is connected to counting units. the inputs of the counters, the code inputs of which are connected respectively to the first and second information inputs of the counter block, the control input of which is connected via the counter control block These are with the inputs of code recording, reset and resolution of the counters, the outputs of which are connected to the corresponding inputs of the block of determining the priority of the counters, the output of which is connected to the pulse output of the block of counters.

.one

The invention relates to an electric electronics, namely to control of converter converters operating from an alternating current network, using digital information processing methods, and can be applied in an adjustable DC motor.

A device for controlling a thyristor converter is known, which contains a clock pulse generator, null organs, clock counters, analog input signal-to-code converters, logic blocks, and code comparison circuits and signals for switching the valves on when tl3 codes are equal. The presence of converters analog signal in the code and an electron on the frequency tuning of the clock, which reduces its accuracy.

The closest in technical essence to the invention is a device for direct digital control using a microprocessor, a dual thyristor converter of alternating current to a constant, containing a microprocessor, a software set device, an external clock, a zero current sensor, an input device for synchronizing with a three-phase current network, an output device for controlling thyristors, monostable selectors, a gain unit and distribution of trigger pulses C2J.

A disadvantage of the known device is the presence of a monostable selector and an external clock, used by the microprocessor for polling the input device at some sufficiently high frequency, which leads to a decrease in the accuracy of the voltage and current control of the valve converter. Another disadvantage is the use of one of the internal registers of the microprocessor as a counter for counting the unlocking angles of the thyristor bridge gates. This leads to the microprocessor loading by unproductive work in

as a pulse counter and, therefore, reduces the possibilities of using the microprocessor to calculate, select and implement various control laws for valve 4 transducer.

The purpose of the invention is to spread the functionality of the device by reducing the raspberry time.

spent by the microprocessor on the control of the angle of unlocking the valves.

The goal is achieved by the fact that a device for controlling a valve converter containing a master clock generator, a microprocessor computing unit including a two processor interrupt with two interrupt inputs, a software master block, a parallel input block and two parallel output blocks, an unlocking distribution unit. pulses, the outputs of which are intended to be connected to the control, electrodes of the converter valves, and the inputs are connected to the external outputs of the first block and Formations, a block of zero-organs and a polarity phase recorder of a three-phase power supply network, the inputs of which are connected to the power supply network, containing six-informational and pulse outputs, are equipped with a clock counter unit with a clock input, a pulse output, two informational and one the control inputs, the zero-organs block and the phase polarity recorder are equipped with a control input, the six-bit information output of the zero-organs bypass and the phase polarity recorder is connected to the information input block information input, the control output of which is connected to the control input of the null-organ unit and the phase polarity recorder, the pulse output of which is connected via the information input unit to the first microprocessor interrupt input to start the null-organ null service subroutine, information and control outputs the second information output unit is connected respectively to the first and second information4 and to the control inputs of the meter block, the clock input of which is connected to the output of the master clock pulse and pulse output to the second microprocessor interrupt input to start the interrupt service routine from clock counters.

The block of zero-organs and the phase polarity recorder contains six channels for converting information about the state of the phase polarities of the three-phase power supply network with a series-connected zero-organ and driver of synchronization pulses in each of the channels, an isolation transformer whose primary phase windings are connected in a triangle and connected to the supplying network., and the secondary connected in a star and connected to the corresponding pairs of null organs, one for positive and one for negative values corresponding linear supply voltage in each pair, controlled six-bit register on six 2Is elements with six-bit information input and control output and six-input element 6INE, with zero-outlets connected to the six-bit information input of the controlled register, the output of which is connected to the information output the control input of which is connected to the control input of the register, while the outputs of the zero-organs are connected via the corresponding synchronization pulse shaper rows bi-NO element whose output is connected to the pulse output unit.

The clock pulse block contains two non-reversible subtracting clock counters of the anodic and cathodic groups of the bridge valve converter, respectively, a meter control unit and a meter priority determination unit, the clock input of the block connected to the counter inputs of the counters, the code inputs of which are connected to the first and second information inputs respectively a block of meters whose control input is connected via a meter control block with code write, reset and enable inputs The counting of the counters, the outputs of which are connected to the corresponding inputs of the block for determining the priority of the counters, the output of which is connected to the pulse output of the block of counters.  FIG.  1 is a functional diagram of a device for controlling a three-phase bridge valve converter; in fig.  2 is a schematic diagram of a null-organ block and a phase polarity recorder; in FIG.  3 - time diagrams of voltages and currents, which explain the operation of the device; in fig.  A - block diagrams of the algorithms of the main part of the control program and subroutines for servicing of preggs.  The device contains a block 1 of null-bodies and a polarity recorder of the phases of a three-phase mains supply, a microprocessor computing unit 2 (microcomputer control, microcomputer), a software master unit 3, a microprocessor 4 with an interrupt system, a block 5 of parallel input of information, blocks 6 and 7 of parallel information output, pin 8 control address 9, data bus 10, microprocessor arithmetological-logic device 11, microprocessor control memory device 12, microprocessor operation control device 13, microprocessor interface 14, microprocessor microprocessor input 15 from the null-organ block and phase polarity recorder, microprocessor interrupt input 16 from the counter block, clock counters block 17, clock 18 clock pulses, cathode and anode counters 19 and 20 clock pulses valve converter, respectively, meter control unit 21, counter priority determination unit 22, information inputs 23 and 24 of the meter block, control input 25 blocks.  the counter, the block 26 of the distribution of the trigger pulses, the information output 27 of the block of zero-organs and the phase polarity recorder, the channel 28 for entering information about the unlocked angle of unlocking, the channel 29 for inputting a discrete feedback signal, the pulse output 30 of the zero block -organs and polar phase recorder, output 31 of the parallel input information block interrupt, control input 32 of the zero-organ block and phase polarity recorder, separation transformer 33, polarity information channels 34-39 The three-phase power supply voltages, 6S-40SH-40 input logic, controlled register 41, separation diode 42, resistors 43 and 44, reference diode 45, base 46 and collector 48 resistor-normalizer bias resistors 47, bias-normalizer bias resistor, transistors 49, capacitor 50, differentiating circuit resistor 51, isolation diode 52, basic 53 and collector 54 resistors.  Transistor 55, register control input 56 56, amplifier 41 with amplifier 57, synchronization pulse generator 58.  The device is intended for digital microprocessor control of a valve converter.  The power part of the valve converter is a rectifier hexent. A bridge consisting of anodic and cathodic groups of controllable gates, for example, thyristors (Fig. 1) Bridge AC clips are connected to a three-phase network.  A rectifying bridge feeds, in the general case, an active-inductive with counter-emf load.  Since all gates of the bridge are controllable, the bridge is fully controllable and symmetrical.  The control electrodes of the thyristors are connected to the corresponding outputs of the distribution unit of the trigger pulses of the proposed device.  The input information for the proposed device are linear voltages of a three-phase mains supply.  e (b and (. , UPC, and their inversions U, Uct ,, Ug, (.  .  Each of these six voltages has its own null organ, which are combined in block 1 of nullorgans and the phase polarity recorder (Fig.  2).  The inputs of the zero-organs are connected with the corresponding phases of the three-phase mains supply, and the outputs are connected through special forma- tion and logic circuits to the input of the input device of the microprocessor computing unit 2.  The microprocessor computing unit 2 is a programmable, real-time controlling specialized computing device, which includes a program-specifying unit 3, a microprocessor 4, an input unit 5 and an information output units 6 and 7 connected by buses 8 management addresses 9 and 10 data buses.  As such a computing unit, a miniature computing machine (microcomputer, microcomputer) can also be used, implemented on the basis of any specific microprocessor set.  The programming unit 3 is a combination of a reprogrammable memory device and a memory device 1 and serves for storing the work program, constants and variable data received from external devices and in the calculation state.  Microprocessor 4 consists of standard nodes: the VIS register arithmetic logic unit 11 of the control memory device 12, the control unit for performing operations 13 and the interface 14 (matching device) for connecting the microprocessor with the address, data and control bus.  The BIS control for executing operations 13 includes a microprocessor prerange system, which has two inputs 15 and 16 as separate buses.  The operation of the main program of the device can be interrupted either by the action of block 1 (from null-organs) at input 15, or from block 17.  program-controlled input counters, 16.  In this case, the microprocessor proceeds to the appropriate preggean service routine.  The clock counters block 17 contains two binary non-reversible subtractive counters 19 and 20 clock pulses, the counter control block 21 and the priority of the counter priority block 22.  Counters 19 and 0 can be loaded with binary codes and controlled programmatically via address 9 buses, data 10 and control buses 8 through a parallel information output unit 7.  For this, the information outputs of Zlok 7 are connected to the information inputs 23 and 24 of the counters, and the control output to the input 25 of the counter control unit 21.  Counters 19 and 20 serve to count time intervals corresponding to specified or calculated values; -it angle unlock valves.  Counter 19 serves to count the angles of unlocking the cathode group valves of the bridge, and counter 20, the anode group.  Counters 19 and 20 count clock pulses from a master high-frequency generator 18 clock pulses, the output of which is associated with the counting inputs from the cetches.  The outputs of the counters are connected to the inputs of the counter priority determining unit 22, the output of which forms the pulse output of block 17, which in turn is connected to the interrupt input of microprocessor 4 to start the subprogram for servicing computing units 2 from counters 19 and 20 clock pulses.  Each of the counters 19 and 20 is irreversible, synchronous, and equipped with a trigger for the end of the counting. The counting inputs of the counters 19 and 20 are combined and connected through an element of the resolution resolution. with clocking input block 17.  The information inputs of the individual triggers of each of the counters 19 and 20 will display the information parallel code input to load the initial code of the measured unlocking angle.  Code counters 19 and 20 are connected respectively with information inputs 23 and 24 of block 17. The control input 25 of the unit 17 is connected via the counter control unit 21 to the recording inputs (set), reset and enable the counters 19 and 20.  The outputs of the trigger end triggering triggers 19 and 20 are connected to the corresponding inputs of the meter priority determining unit 22, and the output of the last item. connected to the pulse output of block 17.  The unit 22 for determining the priority of the counters can have a different design and can be implemented, for example, according to the standard 2ILI logical separation scheme.  In this case, it carries out an equal priority of the counter of 20 clock pulses. The accuracy of the angle adjustment is unlocked depending on the output frequency of the clock pulse generator, which is selected from t to. , 10 kHz, and on the number of binary bits of the counter, which ranges from 8 to 12.  Block 26 serves to finally form, amplify, and distribute and unbolt a pulse. on the converter valves.  For this, the information output of the microprocessor 4 is connected by 8–10 pins to the input of the pulse distribution unit 26, through the unit 6 of the parallel output of the discrete information.  The parallel input unit 5 serves to input discrete information into the microprocessor module and has several inputs (input channels) specified by their addresses: channel 27 for inputting discrete information from the phase recorder of the phases of block 1, channel 28 for entering information about the unlocked angle value, 2.9 channel for inputting a discrete feedback signal on current or voltage of the converter; and so on. P.  The input unit 5 also has an input 30 and an output 31 for transmitting a pulse interrupt signal produced by an external unit.  In the proposed device, the interruption of the program is carried out at the onset of the moment of zero crossing of any linear voltage of the three-phase supply network from the pulse, which is formed by the zero-bodies of unit 1.  For this, the pulse output of the unit 1 is connected to the input 15 of the microprocessor control device 13 via the input 30 and the output 31 by interrupting the input unit 5.  Channel 32 connecting blocks 1 and 5 serves to transmit control signals to the input of microprocessor computing unit 2 to block 1.  The null-organ unit 1 and the phase polarity recorder contains (FIG. 2) separation matching transformer 33, six channels 34-39 of converting information about the state of the polarities of the phases of the supply voltage with the series-connected zero-body 57 and the driver 58 of the synchronization pulses, in each channel, controlled by a six-bit register 41 in six logic elements 2I with six-bit information input and output 27 and input 56 of control and six-input logic element BI-HE 40.  The primary windings of the phases of the isolation transformer 33 are connected to a standard delta circuit and connected to a three-phase supply network, and the secondary ones are connected to a star and connected to the input terminals of the zero-organs.  Of the six zero-organs of block 1, three belonging to channels with numbers 34, 36 and 38 register the transfer of supply linear voltages from negative to positive values, and the remaining three belonging to channels with numbers 35, 37 and 39 from positive to negative values .  The outputs of the null organs are connected via transistor pulse drivers to the corresponding inputs of the six-input logic element of an AO that implements the BI-NO logic.  The output of this element is the pulse output 30 of unit 1 and is connected to the input by interrupting input device 5.  The internal structure of the polarization phase information channels 3439 of the phases of the mains voltage and the null bodies and shapers of the synchronization impulse included in them can be different.  FIG.  2 presents one of the simplest variants for performing null-bodies and formers.  The zero-organ of any of the channels 3439 for converting information about the state of the polarities of the phases of the supply voltage contains, in turn, an input circuit and a transistor normalizer.  For example, the null-organ 57 of channel 35 contains a separating diode 42 with a current-limiting resistor 43, a reference diode 45 with a current-limiting resistor 44, and an amplifier with a transistor 49.  A chain of series-connected isolation diode 42 and a resistor 43 is connected between the beginning of the winding of the corresponding phase and the common point of the star star of the secondary winding of the transformer 33.  A chain of series-connected resistor 44 and the reference diode 45 is connected in parallel to the resistor 43.  The input circuit is designed to match the magnitude of the input alternating voltage with the level of the input signals of the transistor amplifier of the normalizer and TTL logic and to generate a signal of logical 1 during the first or second half period of the alternating voltage, t. e.  to select the desired half period.  At the output of this circuit, t. e.  on the reference diode 45 conducting the current in the forward direction, a square pulse of one or another polarity is obtained depending on the selected half period.  The transistor amplifier-normal-g contains a 49 np-transistor, a base 46 and a 48 collector resistors, as well as a bias resistor 47.  The amplifier-normalizer input is connected in parallel to the diode 45.  The normalizer amplifier serves to amplify and limit the pulses fed from the input circuit, as well as to bring them to the levels of logic 1 and logic O.  The amplifier circuit of the normalizer varies depending on which half-period of the input variable voltage it forms a logical signal.  If it generates a logical 1 signal in the first half period, and a logical O signal in the second, it is performed according to the emitter follower circuit.  However, it does not have a bias resistor, and the load resistor 48 is in the emitter circuit.  According to this scheme, zero-organs of channels 34, 36, and 38 are made.  If it generates a signal of logical 1: in the second, half-period, and the signal of logical O in the first, it is made according to the scheme with a common emitter.  At the same time, it is provided with a bias resistor 47, which is connected between the plus 30 bus of the source and the buy, and the load resistor 48 is connected to the collector circuit of transistor 49.  According to this i scheme, zero-bodies of channels 35, 37 and 39 are performed.  A set of six zero-bodies forms a six-channel recorder of polarities of supply voltage phases.  network, having a six-bit output.   The voltage at the output of any amplifier-normalizer is information; For the transmission of this signal, the output of any amplifier of the normalizer is connected to the information input of the corresponding two-input element 2I of the control information transfer register 41.  The composition of any of the channels 34-39 information conversion 34 includes a synchronization pulse driver.  For example, the synchronization pulse driver 38, which is part of channel 35, contains a reference circuit and an output transistor amplifier.  Differentiating circuit; Consisting of after; An optically connected capacitor 50 and a resistor 51 are connected between the output of the nulborgan 57 (collector of transistor 49) and the common wire.  It serves to form narrow voltage pulses at the moment of transition of the linear voltage Cdc through zero value.  The output transistor amplifier is made according to the scheme with a common emitter and contains a transistor 55, a base 53 and a collector 54 resistors.  The input of the amplifier transistor through the separation diode 52 is connected in parallel to the resistor 51 of the differentiating circuit.  Isolation diode 52 serves to block the negative pulse generated by the differentiating circuit.  The transistor 55 opens only at those times when positive narrow pulses arrive from the latter.  Accordingly, in the same time intervals at the output of the amplifier, t. e1 on the collector of transistor 55, narrow voltage pulses are produced, inverted relative to the positive supply voltage level + 5V.  The device of the other channels of rtpeforming the information about the state of the polarity of the phases of the supply voltage is similar, the differences are only in the connection point of the input circuit, the conduction direction of the separator 42 and the reference 45 diodes and the configuration of the amplifier-normalizer circuit.  The outputs of the pulse formers of all six channels 34-39 of information conversion are connected to the corresponding inputs of the six-input logic element 6I-HE 40, which is about. there is an OR logic for the inverse values of the signals at its inputs.  Consequently, at the output of the element 40, a series of narrow pulses of positive polarity are produced, the frequency of which is equal to six times the frequency of the supply network.  Each of these pulses occurs at the moment when any of the linear voltages of the network passes through zero.  The output of the element 6I-NOT 40 forms the pulse output 30 of unit 1, which in turn is connected to the pulse input 5 of the information input unit 5, the output 31 of which is connected to the input 15 of the interrupted microprocessor 4.  When a synchronization pulse arrives from output 30 of block 1, an interruption of the main processor program occurs and the subroutine of the null-organs interrupt service is started.  The control register 41 of information transfer is executed on six two-input togic elements 2I.  The first inputs of these elements form the information input of the register 41 and are connected to the outputs of the corresponding zero-organs of channels 34-39.  The second inputs of these elements are combined) To control control register 41, channel 41, the control channel 32 of block 1, through which the input signal from block 3 of parallel input of information is transmitted.  The six-bit output of the controlled register 41 is the information output 27 of the null-organ 1 unit and the phase polarity recorder, which is connected to the information input of the information input unit 5.  The device for control of the converter works on the next

in a way.

After turning on the power supply and starting the program, the program-generating unit 3 of the microprocessor computing unit 2 performs the initial reset and installation of all external devices and units, turns on the interrupt system of the microprocessor 4 and generates a certain control law. The set value of the unlocking angle, for example, in a binary code, is read by the microprocessor through the input block 5 via channel 28, is adjusted in accordance with the feedback signal entered through channel 29, according to the virtual control law, and prepared for data control 23 and 24 program control counters 19 and 20.

The block 2 on the organ and the phase polarity recorder at its output 30 expires after each moment of transition of one of the line voltages of the network through the zero level a narrow pulse coming through the input device 5 to the input 15 of the microprocessor 4 interrupt system. since the time delay of the appearance of these pulses after the corresponding moments of crossing the zero level is insignificant, then practically these pulses can be considered the consistency of the valves of the diode bridge.

At any given time at the inputs of the register. 41, there is information about the current state of the polarity of the phases of the linear voltages. This information is read by the microprocessor by a 6-bit parallel code on channel 27 through device 5 by applying a logical 1 signal (Input signal) to control input 56 of register 41 (Fig. 2). This code will correspond to the following nullorgans and linear stresses (see Table 1).

The data output device 6 is connected to the control electrodes of the power bridge gates through the drivers of the unloading pulse distribution unit 26 in such a way that each bit (bit) of the output byte of information corresponds to a specific bridge gate. The correspondence of the bits of the code inserted by the microprocessor module 2 through the output device 6 and block 25 to the controllable bridge valves is established by the table. 2

In the interval of each of the mains voltage zones, only one, next, valve of the bridge can be switched on, while the previous one falling with moments of natural unlocking of the valves. The pulses generated by block 1 play the role of the synchronization pulses of a device operating with variable supply voltages. The entire period of change of each supply voltage with synchronization pulses is divided into six intervals - network voltage zones. Each zone is characterized by a specific code on the code of the phase polarity recorder (RPF) of block 1. In the interval of the duration of one zone, the value of this code remains unchanged. If the semiconductor power bridge of the valve converter (VP) was uncontrollable, i.e. Not performed on thyristors, but on diodes, then with the onset of each successive zone, the next valve would enter the conducting state. From this it follows that the zones of the mains voltage can be numbered in the order in which the entry into the conductive gate turns on, continues to conduct, and the gate that preceded the previous fYi goes out of the conduction state. In tab. 3 indicates which byte code of the input information corresponds to the byte code of the output information, i.e., such gates can be turned on in a particular zone. From tab. 3 it follows that the unit state of the output code bit corresponds to a high voltage level at the control electrode of the thyristor, to zero state, the absence of voltage. At certain points in time, single codes through the output device 6 and then removing them, the microprocessor, in the sequence specified by the program, and in accordance with the input actions, switches on the selected gates, i.e. valve converter control. The microprocessor module 2 operates during the whole period of operation of the proposed device for controlling the valve converter from the moment of its programmed power on, stored in its memory, in accordance with the algorithm shown in FIG. 4. As follows from FIG. 4, the device operation algorithm consists of three parts, which correspond to the main program and two interrupt routines. The main program; I correspond to the blocks A1-A6 of the .cxeMbf block of the algorithm. The subroutine of the interruption from zero-bodies corresponds to the blocks A7-At4, the subroutine of the interruption from program-controlled counters (CCP) - 6LOKS.A15-A18. The program operates cyclically, in cycles, the beginning of each cycle corresponds to the leading edge of the synchronization pulse (Fig. 3). Each zone of the mains voltage corresponds to one control cycle, in which the value of the angle of unlock is calculated, and the corresponding output code is determined and released: unlocked valves. Synchronization pulses, the arrival of Yermi from the null-organs of block 1, interrupts the main program six times in a period. In each cycle, the microprocess 1 8116 sor reads system information, for example, through channel 28 — the specified value of the output coordinate (voltage or current at the output of the VI), the operating mode code, etc. Suppose, for definiteness, the valve converter operates in the voltage regulation mode U constant In this case, the channel 28 reads in binary code the set value of the output voltage Uof3 "A. .. On channel 29, the value of the feedback signal, i.e., is read from the sensor in channel code. technological information about the monitored parameter. In our case, this parameter is the actual output value. voltage 11. Let us assume that the VP control unit operates with open-loop feedback (KO, (O), and the control law corresponds to the development of a stepped input signal of a constant value of infinite duration, fed to the input 28 at the time t ,. The following is a description of the algorithm blocks, corresponding to the flowchart in Fig. 4. Block A1 Beginning. This block corresponds to the start of the main part of the program's control box. Block A2 Initialization. In this block, the microprocessor module 2 performs the initial reset, installation and initial state all x external devices and blocks and preparation of working memory cells, turns on microprocessor breaks system 4 and includes blocks 1 and 17 capable of causing interrupts. Block A3 Determining the initial value of the unlocking angle. The specified initial value U, for example, in binary code is read by the microprocessor 4 through the input device 5 via channel 28. The initial value of the unlocking angle is calculated using the formula JI, .- ... .... |, arccos is further multiplied by the corresponding scaling factor and is prepared for incrementing it to the information input program. mmno-controlled counter block 17. Block 19 A4 Receiving input information. This unit and all. the subsequent ones belong to the cyclically repeating part of the program, in contrast to the A1-AZ blocks, which characterize its initial part. Channel 28 reads the set value of the output voltage of the Ujgp CU. Channel 29 reads the feedback signal, i.e. Technological information about the controlled parameter. In our case, this parameter is the actual value of the output voltage U. Block A5 Calculation of the next value of the unlocking angle. According to the known and calculated values, in accordance with the chosen law of regulation, the angle d is unlocked for the next valve. Since where Od is the linear voltage of the network. Then, the current value of the angle -d is multiplied by the coefficient of recalculation into the code of the time interval assigned to the information input of the counter 19 or 20, Block Ab Waiting for the interrupt. Since all the computational and preparatory operations are completed, it gives the command to allow the superprocessor 4 to be enabled and then go back to block 6, i.e. wait for an interrupt. Block A7 Termination from null-organs. When a linear supply voltage reaches a zero level, unit 1 of null organs and the phase polarity recorder interrupts a narrow pulse at its 30, which affects through the parallel exchange unit 5 to input 15 of the microprocessor interruption system 4. The subroutine starts Interruption from zero-bodies. Block A8 Reception code from the RPF. The microprocessor receives a digital 6-bit code from the polarity recorder of the phases of block 1 through kangsha 27 via the 5 input device. J 8118 Block A9 Cathodic valve zone. Groups The microprocessor analyzes the phase polarity status code and determines from it which zone of the valve is in place at a given time. If there is a zone of the cathode group valve (with an odd number), then the program proceeds to block A12, if not, then to block A10. Block A10 Zone valves anode group. The microprocessor analyzes the state code of the polarity of the phases and determines from it whether the zone of the anode valve of the anode group (with an even number) is going at that moment. If there is an even-valve zone, then the program proceeds to block A13, if none of the zones is identified, then to the block AI. All block Emergency stop. Since the microprocessor did not identify the zone of any of the gates, this means that the five code from the code coincides with the reference codes of the zones and, consequently, there are some features in the operation of the equipment. The ability of the program to enter the All block allows the software to organize the following functions of the device: diagnostics of the state of the input signal path (supply network, blocks 1 and 5); automatic search for a faulty node; print or display message to attendants; switching operations, emergency shutdown; alarm activation, emergency stop. In the above example, only Emergency Stop is provided. Block A12 Select the next valve of the cathode group. Launch PUSG. The unit operates if zone 1, 3 or 5 is present. The code from table C01 is recorded in the memory cell of the code issued on the control of the thyristor electrodes. 3, respectively, 1, 3 or 5 valves to be turned on after testing with Wt. Then, a control panel containing the address (bit 15) and the binary code of the time interval in the low-order bits of the programmable counter 19 (PUS1) are output and sent via channel 23. At the same time, on channel 25, the Signal output, after receiving which ACN1 is triggered.

UNIT A13 Selection of the next anodic valve group. Launch PUS2.

The block works if zone 2, 4 or 6 is present. The code from table C01 is written into the memory cell of the code issued to the control electrodes of the thyristors. 3 respectively 2, 4 or 6 valves to be included in this zone. Then, a control code is generated and entered on channel 24 containing the address (bit 15) and the binary code of the time interval in the lower bits of the program-controlled counter of its counter 20 (11US2). Simultaneously via channel 25, the signal Vsod appears, after receiving which PUS2 is triggered.

Block 14 Exit interrupt Hd calculation of the angle of unlocking.

The microprocessor exits the null-organ interrupt mode, and the program proceeds to block 4, i.e. to receive input information and then calculate the next value of the angle unlock.

Epok A15 Prerage from PUS1 or PUS2.

After starting, the selected counter 19 or 20 begins to subtract one from the recorded starting code with the arrival of each clock pulse from generator 18 and after counting the time interval corresponding to the calculated unlocking angle at zero time it acts through priority circuit 2 (circuit OR) and input 16 microprocessor interrupt system 4. The processor interrupts its operation and goes to the subroutine Interrupt from ПУС1 or ПУС2 (block А15).

Block A16 Reset ПУС1 or ПУС2.

The first operation of the subroutine subroutine from the counters is the reset of the interrupt triggers ПУС1 or ПУС2, which goes to the control unit 21 of the meter control. These triggers are reset by the Input signal, received by the microprocessor through the output device 7 at block 21 via channel 25.

Block A17 Turn on the selected, ventil.

In accordance with the code selected. Previously, in the A12 or A13 valve units, the microprocessor outputs, via the data output device 6, to the trigger pulse distribution unit 26, a signal. The voltage on the control electrodes of the valve to be turned on and the previous, turned on, valve for confirming the last-conducting state.

Elok A18 Exit interrupt.

The microprocessor exits the interrupt mode from the program-controlling counters block 17, and the program returns to the command in front of which the interruption occurred.

With the arrival of a crash pulse from the next, next, nullorgan of block 1, the entire cycle of operation is repeated according to the flowchart from the block A6 through the subroutine from the null organs (blocks A7-A14), blocks A4, A5, A6 and the interrupt routine from PUS1 or ПУС2 for the zone of the next activated valve.

In the device according to the invention, in comparison with the known one, there are two counters for counting the angles of unlocking the six valves of the converter bridge, one for the cathode group, the other for the anode group of valves. The counters are started in moments of natural unlocking alternately, which, in the presence of software control, increases the reliability of the device and the valve converter.

The advantage of the device is the possibility of changing the law of control of the valve unlocking angle according to a program defined in advance or corrected in the process of control, which is a prerequisite for building adaptive or self-adjusting systems based on it. The ability to work on a variable, corrective program increases the flexibility of controlling the valve converter and, consequently, expands the control functionality.

The advantage of the proposed device is the release of the microprocessor from the elementary function of counting the time intervals, which occupies most of the time (up to 98%) of the minutes and sharply reduces the efficiency of using the processing element in the device. This function of counting the number of clock pulses for measuring the delayed switch-on interval of the selected valve is assigned in the device to the usual 21. external binary clock counters. The processor is assigned the function of a higher level, the function of controlling the angle of unlocking of the converter valves, which consists of the following smaller functions: F1 - control of the operation of the system of intercoms of the processor itself; F2 - reception of a given value. the angle of unlocking or a given law of its change, as well as information about the value of the feedback signal; FL - control of the reception of information about the state of voltage of the network; PD - analysis of input information and selection of the next unlocked vent l; F5 - the calculation of the required angle o Pirani for the selected valve; FB control over the operation of external clock pulses, including: F6.1 — select the appropriate counter; F.2, enter the unlock code in the selected counter; Fb. 3, run the selected counter F6.4, receive the interrupt (i.e. from the bank stating that the specified time interval has already been counted), f6.5 - resetting the interrupted sirnal counter, code discharge (bit) -Logic variable on the register inputs 41 Zero-organ number (Fig. 2) 34 39 I Chart (fig. 3) H06 H05 Linear voltage AB CB

Bit size (output)

Q5 code Number of the turned on valve B6

table 2

03

02

00

01

AT 4

OT

IN 1

B2 1 f7 - signal to turn on the selected valve. The functions of the processor are listed here, namely, those that are necessary to fulfill the main purpose of the device - controlling the valve converter. When implementing the described interrupt-based control algorithm, these functions take up only about 2.5% of the CPU time. In this case, the external block of counters, performing the function of clock pulses of the external master oscillator, operates continuously and in parallel with the processor. As a result of this organization of hardware and software, the processor can be additionally assigned the functions of diagnosing the technical state, monitoring process parameters, signaling, issuing messages to maintenance personnel, searching for the optimal mode, etc. This leads to an increase in the functionality of the device by reducing computer time, spent by the microprocessor to control the angle of unlocking the valves. 4Table 38 37 NO4 NOZ CA VA 11B1 12V2 13VZ o4V4

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Claims (3)

1. DEVICE FOR MANAGING A FAN INVERTER, comprising a clock master, a microprocessor computing unit, including a microprocessor with two interrupt inputs, a program and master unit, a parallel input unit and two parallel information output units, an output pulse distribution unit, the outputs of which are intended for connection to the control electrodes of the converter gates, and the inputs are connected to the outputs of the first information output unit, the zero-organ unit and the recorder the polarity of the phases of a three-phase power supply network, the inputs of which are connected to the power supply network, which contains six-bit information and pulse outputs, with the aim that, in order to expand * the device's functional capabilities by reducing machine time spent by the microprocessor to control the angle of unlocking the valves, it is equipped with a block of clock counters with a clock input, a pulse output, two information and one control inputs, a block of null organs and a phase polarity recorder equipped with a control input, the six-bit information output of the null organs block and the phase polarity recorder is connected to the information input of the information input block, the control output of which is connected to the control input of the null organs block and the polar recorder - -S of these phases, the pulse output of which is connected through the information input unit to the first microprocessor interrupt input to start the interrupt service routine from null organs, the information and control outputs of the second information output unit under connected respectively to the first and second information and control inputs of the counter block, the clock input of which is connected to the output of the master clock generator, and the pulse output to the second microprocessor interrupt input to start the interrupt service routines from the clock counters. 2. The device according to claim 1, characterized in that the block of zero-organs and the phase polarity recorder contains six channels for converting information about the state of the phase polarities of the voltages of the three-phase supply network with series-connected zero-organ and synchronization pulse shaper in each channel, a separation a transformer, the primary phase windings of which are connected in a triangle and connected to the supply network, and the secondary ones are connected to a star and connected to the corresponding pairs of null organs, one for positive and another for negative values of the corresponding linear voltage of the supply network in each pair, a controllable six-bit register on six 2I elements with six-bit information input and output and control input and a six-bit one: element 6I-NOT, with zero-outputs connected to the six-input information input of the controlled register, output which is connected to the information output of the unit ·, the control input of which is connected to the control input of the register, while the outputs of .null organs through the corresponding formations The pulses of synchronization are connected with the inputs of the 6I-NOT element, the output of which is connected to the pulse output of the unit. 3. The device according to claims 1 and 2, characterized in that the block of clock counters contains two non-reversible subtracting clock counters of the anode and cathode groups of the bridge valve converter, respectively, a counter control unit and a meter priority determination unit, wherein the clock input of the block is connected to the counting counter inputs, the code inputs of which are connected respectively to the first and second information inputs of the counter block, the control input of which is connected through the counter control block and with inputs of code recording, reset and resolution of the counters counters, the outputs of which are connected to the corresponding inputs of the counters priority determining unit j whose output is connected to the pulse output of the counters block. .1