SU1132293A1 - Counter with check - Google Patents

Abstract

A CONTROL COUNTER containing a counter, the group of outputs of the bits of which is a group of information outputs of the counter, characterized in that, in order to increase reliability by recovering the counter on failure, a register, an adder, a comparison unit, a group of NOT elements are entered into the counter AND element, NAND element, two NOT elements, three OR elements, the group of information inputs of the register is connected to the group of outputs of the counter bits, the first group of inputs of the comparison block, the inputs of the elements NOT groups whose outputs connect They are not connected to the first group of inputs from the mapper, the second group of inputs of which is connected to the group of register codes, the second group of inputs of the comparison unit, the group of information inputs of the counter, the installation input of which is the installation input of the counter, the first synchronized input of which is i And, the output of which is connected to the first input of the first element OR, the second input of which is connected to the input of the first element NOT and is the second synchronous input of the counter, the third synchronized input of which is connected to the input the house of the second element is NOT, with the first input of the second element. OR, the second input of which is connected to the output of the second element AND is the output of information about the counter failure, the output of issuing information about the register failure is connected to the output of the third element AND, the second input of the first element AND, controlling the input of the counter, the counting input of which connected to the output of the first element OR, the output of the first element is NOT connected to the first input of the third element AND, the second input of which is connected to the output of the third element OR, the first input U d N9 of which is connected to the output of the first digit of the adder, gr Uppa outputs of which bits from the second to the rt-th are connected to the group of inputs of the ECO & 9 of the AND-NOT, the output of which is connected to the second input of the third element OR, the output of the second element OR is connected to the synchronous input register, the output of the second element is NOT connected with the first input of the second element I, the second input of which is connected to the output of the comparison unit.

Description

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The invention relates to digital automation and monitoring and measurement technology, and is intended to restore a fault counter.

A device for controlling counters is known, which contains a pulse distributor, a trigger, controlled counters, source coherent source decoders: maximum filling decoders, two groups of OR elements, AND element, pulse generator, display elements, OR NON W element.

A disadvantage of this device is the impossibility of recovering the counters on failure.

The closest in technical essence to the invention is a major-redundant device containing redundant blocks, the main synchronization inputs of which are connected to the first synchronization bus, and the bit inputs to the corresponding bit inputs of the majority elements block whose outputs are connected to the device outputs all the bit outputs of the majority elements block are connected to the installation inputs of the corresponding bits. Dates of all reserved blocks, whose auxiliary synchronization inputs are connected to the second synchronization bus.

The disadvantage of such a device is that redundancy and majoritarianization are used to achieve high reliability and reliability. This leads to a significant complication of the scheme, especially when the size of the reserved blocks is large. A short-term failure on the device's output bus is also possible, which may lead to the establishment of all redundant blocks in the wrong state.

The purpose of the invention is to increase reliability by restoring the counter on failure.

The goal is achieved by the fact that a register with a counter, whose output group of bits is a group of information outputs of the counter, is entered into a register, an adder, a comparison unit, a group of NOT elements, three AND elements, an AND-NOT element, two NOT elements. , three elements OR, at 322932

than the group of information inputs of the register is connected to the group of outputs of the counter bits, the first group of inputs of the comparison block, the inputs of the elements NOT the groups whose outputs are connected to the first group of inputs of the adder, the second group of inputs of which are connected to the group of outputs of the register, the second O inputs of the block comparison, a group of information inputs of the counter, the installation input of which is the installation input of the counter, the first synchronized input of which is connected to the first input of the first element I, the output of which is connected to the first input Odom first OR gate, a second input coupled to the input of the first element is 20 FIE and vtorm a clock terminal of the counter, the third clock terminal coupled to an input of the second NOT member with the first input of the second OR gate, the second input of which is connected

25 with the output of the second element AND is the output of information about the counter failure, the output of the information about the register failure is connected to the output of the third element AND, the second

0 the input of the first element AND, the control input of the counter, whose counting input is connected to the output of the first OR element, the output of the first element is NOT connected to the first input of the third AND element, the second input of which is connected to the output of the third OR element, the first input of which is connected to the output of the first adder bit, output group

(j bits of which from the second to the th-th are connected to the group of inputs of the NAND element, the output of which is co. dinene to the second input of the third element OR, the output of the second element

5 OR is connected to the register clock input, the output of the second element is NOT connected to the first input of the second element AND, the second input of which is connected to the output of the comparison unit.

Q H FIG. 1 is a functional diagram of the device; FIG. 2 - time diagrams that show his work.

The device contains a counter 1, 5 register 2, adder 3, block 4 comparisons, a group of 5 elements NOT, an element AND 6, an element AND 7, an element AND 8, an element NOT 9, 10, an element OR 11, an element OR 12, a group of information device outputs 13, output 1 of information about the failure of the error information counter, register output 15, first device synchronization input 16, second device synchronization input 17, device synchronization third input 18, device installation input 19, element 20 OR element 21 AND -NOT. Register 2 is designed to record and store information coming from the output of counter 1. Adder 3 is designed to sum the information from the output of register 2 with an inverted group of 5 items NOT information from the output of counter 1. When the device operates in the adder 3, the summation of the direct the code of the previous state of counter 1 with the inverse code of the subsequent state of counter 1. In the absence of the failure of counter 1, with such a summing up, the output of the lower bit of the adder 3 will always be a logical zero, and at the higher bits dah - units. Comparison unit 4 is designed to compare information at the outputs of counter 1 and register 2. The first output 14 of the device’s failure is intended to issue information | About register 2 failure. The second output 15 of the device’s output is intended to provide information about counter 1. For synchronous inputs 16-18 the same sync pulses are received, but with a shift in time (Fig. 2a, fi B). The counter operates as follows. The counter works in three stages. . The first stage takes place at time T1 (Fig. 2). Before work starts, the counter 1 is reset to the zero state. A positive differential pulse arriving from the third synchronous input 18 of the device (Fig. 2) records the zero state of the counter 1 to the register 2. In the comparison block 4, the information from the outputs of the bits of the counter 1 and the register 2 is compared. register 2 at the output of block 4 comparing with Vits positive 93. pulse difference (Fig. 22), which is fed to the input of the And 8 element, to the other input of which the inverted signal arrives from the third synchronous input 18 of the device (Fig. 2). At the output of the element And 8, we get a positive pulse difference (Fig. 2e), which will overwrite information from the outputs of counter 1 in register 2. We assume that after the second recording in register 2, the information on its outputs will fully correspond to the state of counter 1. Second stage takes place at time t2. In this case, the meter works as follows. A positive differential pulse arriving from the second synchronous input 17 of the device (Fig. 2 b), the counter 1 is modified to the first state. In adder 3, the code 0000 is output from the register .2 with the code 1110 from the outputs of the group of 5 NO elements (example for a 4-bit counter 1). At the output of the low bit of the adder 3 there will be a logical zero, and at the high bits of the bit - ones. If there is a fault at the outputs of counter 1 at the output of the element OR 20, the logical unit that goes to the input of the element is AND 6, to the other input of which the signal from the second synchronous input 17 of the device inverted by the HE element 9 arrives. At the output of AND 6, a positive pulse difference appears (Fig. 2), according to which information from the outputs of register 2 is recorded into counter 1. At the same time, counter 1 is set to the previous (zero) state. In the adder 3, the code 0000 is coded with the code 1111, while the output of the element And 6 will contain a logical unit (Fig. 2), which will keep the element And 7 in the open state. In the third stage of the p% bots counter, the counter 1 is modified according to a positive differential pulse coming from the first input of the device 16 through the open element AND 7 (Fig. 2 J). In this case, counter 1 is set to the first state.

five . 1132293

The further operation of the meter is pro-cost and has more

proceeds in a similar way. Reliability compared to -sma Thus, the proposed legal-reserved-reserved

Performance requires less hardware.

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Claims (1)

A COUNTER WITH A CONTROL containing a counter, the group of discharge outputs of which is a group of information outputs of the counter, characterized in that, in order to increase reliability due to the recovery of the counter by failure, a register, an adder, a comparison unit, a group of elements are NOT entered, three elements AND , the AND element, two NOT elements, three OR elements, the group of information inputs of the register connected to the group of outputs of the bits of the counter, the first group of inputs of the comparison unit, the inputs of the elements of the NOT group whose outputs are connected to the first group of inputs of the adder, the second group of inputs of which is connected to the group of input inputs of the register, the second group of inputs of the comparison unit, the group of information inputs of the counter, the installation input of which is the installation input of the counter, the first clock input of which is connected to the first input of the first element And, the output of which connected to the first input of the first OR element, the second input of which is connected to the input of the first element NOT and is the second counter clock input, the third clock of which is connected to the input of the second element that is NOT with the first input of the second element. OR, the second input of which is connected to the output of the second AND element and is the output of the counter failure information, the output of the register failure information is connected to the output of the third AND element, the second input of the first AND element, which controls the counter input, the counting input of which is connected to the output the first OR element, the output of the first element is NOT connected to the first input of the third AND element, the second input of which is connected to the output of the third OR element, the first input of which is connected to the output of the first discharge of the adder, the group of outputs p whose second to rtth rows are connected to the group of inputs of the AND-NOT element, the output of which is connected to the second input of the third OR element, the output of the second OR element is connected to the register clock input, the output of the second element is NOT connected to the first input of the second AND element, the second input which is connected to the output of the comparison unit. > two rpynMi, geneindicofo