SU1130874A1 - Correlator - Google Patents

Abstract

A CORRELATOR containing a multiplexer, a subtractor, a recorder whose output is the output of the correlator, a demultiplexer whose information and control inputs are respectively the first information input and the synchronizer input of the correlator, the outputs of the demultiplexer are connected to the information inputs of the corresponding L registers, the reference register a signal whose information input is the second information input of the correlator, a decimal-to-binary converter, whose input is the input of the reference signal length code, the control unit containing the multivibrator, the element AND, the decoder, the one-shot, the element OR, the element 2I-OR, the first and second triggers, the first, second and third counters, the bit outputs of the first of which are connected to the corresponding inputs the decoder, the output of the last bit of which is through one-shot. connected to the clock input of the second counter, the single input of the first trigger and the first input of the OR element, the output of which is connected to the first input of the 2I-1SHI element, the second input of the OR element is combined with the second input of the 2I-1ShI element, the clock input of the third counter and connected to the output of the multivibrator, the control input of which is combined with the first input of the AND element and connected to the single output of the first trigger, the zero input of which is connected to the output of the third counter, the second input of the AND element combined with (P the third input of the 2I-OR and connected to a single output of the second trigger, the zero output of which is connected to the fourth input of the element 2И-OR, the single input of the second trigger connected to the output of the second counter, the installation inputs of which are combined with the installation inputs of the third counter, o. so that, in order to simplify the correlator, it also includes EXCLUSIVE OR elements and counters, whose inputs are connected to the outputs of the corresponding EXCLUSIVE OR elements, and the outputs are connected to the corresponding information the multiplexer inputs, the control input of which is connected to the outputs of the decoder and the one-shot of the control unit, the output of the multiplexer is connected to the first input of the subtractor, the second input of which is connected to the output of the additional code

Description

the decimal code to binary converter, the output of the subtraction unit is connected to the information input of the recorder, the control input of which is combined with the clock input of the first counter of the control unit and the control. the demultiplexer input, the first inputs of the EXTENDER OR elements are combined and connected to the outputs of the multi: vibrator and the element AND control unit, the second inputs of the EXCLUSIVE RSH elements are connected to the outputs, respectively.

30874

the corresponding n registers, the control inputs of which are combined and connected to the output of the OR element of the control unit, the third input of the element AND of which is connected to the output of the reference signal register, the control input of which is connected to the output of the element 2И-OR of the control unit, the setting inputs of the third counter of which are connected to the output of the direct code of the decimal to binary code converter.

The invention relates to information processing devices and can be used, for example, to obtain pulsed seismograms during seismic surveys of oil, gas and other minerals using vibratory sources of elastic oscillations,

A device is known that converts digital seismic information by calculating the correlation functions of a seismic signal, in which the multiplication operation is replaced by summing the logarithms of the factors. Before performing the accumulation of napriHX works, the operations of potentiation and alignment of orders ij are performed.

A disadvantage of this device is a large amount of equipment, due to the presence of logarithmics and potentiation blocks made on permanent memory devices.

The closest to the invention to the technical nature is seismic: a scaled order correlator containing a control unit, a block of ordering and sampling signs, a summator of orders, a summator mantissus, a normalization block, a subtractor, a decoder, registers, multiplexers, demultiplexers, blocks accumulating memory, J2J recorder.

The device is designed so that it performs parallel computation of paired procs in one clock cycle. . .2,

references for M samples of the intercorrelation function, and the results of N clock cycles (N is numerically equal to the length of the reference signal) are summed up in you. the in-built accumulative memory of the channel of volumes in M words about. Therefore, a large accumulating memory is required in this correlator. The input information in this device is used in the floating point format, but only the order of the pre-normalized values of the binary-coded information samples is used for the calculations. As a result, in order to improve processing accuracy, there is a need to pre-adjust the amplitude of the input signals and convert the standard format of the input information to a special order format, which leads to a complication of the device and an additional increase in hardware costs. Thus, the disadvantages of the known device are a significant amount of equipment and, as a consequence, a large power consumption.

The purpose of the invention is to simplify the correlator and reduce the power it consumes. ,

This goal is achieved by the fact that in a correlator containing a multiplexer, a subtraction unit, the recorder whose code is the output of the correlator, the demultiplexer whose information and control inputs are respectively the first information input and the synchronizer clock input, the demultiplexer outputs are connected with the information inputs of the corresponding n registers, the reference signal register, whose information input is the second information input of the correlator, the decimal code converter in binary, the input of which is the input of the reference signal length code, the control unit containing the multivibrator, the AND element, the decoder, the one-vibrator OR element, the 2I-OR element, the first and second triggers, the first, second and third counters, and the outputs the first of which is connected to the corresponding inputs of the decoder, the output of the last bit of which is connected via a single vibration to the clock input of the second counter, a single input of a new trigger and the first input of the OR element, the output of which is connected to the first input element 2И-Ш1И, the second input of the element OR is combined with the second input of the element 2И-ИПИ, the clock input of the third counter and connected to the output of the multivibrator, the control input of which is combined with the first input of the element AND and connected to the single output of the first trigger whose zero input is connected to the output of the third counter, the second input of the AND element is combined with the third input of the 2I-OR element and connected to the single output of the second Trigger, the zero output of which is connected to the fourth input of the 2I-IPI element, the single input of the second trigger The erra is connected to the output of the second counter, the setup inputs of which are combined with the installation inputs of the third counter, are entered the EXCLUSIVE OR and P elements of the counter, the inputs of which are connected to the outputs of the corresponding EXCLUSIVE OR elements, and the outputs are connected to the corresponding information inputs of the multiplexer The main input of which is connected to the outputs of the decoder and one-shot of the control unit, the output of the multiplexer is connected to the first input of the subtractor, the second input of which is connected to the output of the additional Yelnia a decimal code converter in the binary code, Yield subtracting unit is connected to the data input of the recorder control input of which is combined with the clock input of the first counter

the control unit and the control input of the demultiplexer, the first inputs of the elements EARNING OR are combined and connected to the outputs of the multivibrator and the element I of the control unit, the second inputs of the elements EXCLUSIVE EI are connected to the outputs of the corresponding n registers whose control inputs are combined and connected to the output of the element OR of the control unit , the third input of the element And of which is connected to the output of the register of the reference signal, the control input of which is connected to the output of the element 2И-OR of the control unit, the setting inputs of the third The counter of which is connected to the output of the direct code of the converter of the decimal code into the binary one.

Figure 1 shows the block diagram of the device; 2 is a block diagram of a control unit; figure 3 - timing charts of the device.

The device (Fig. 1) contains a demultiplexer 1, q registers 2, control block 3, rj elements EXCLUSIVE OR 4, n counters 5, converter 6 of decimal code into binary, multiplexer 7, block 8 of subtraction, recorder 9 and register 10 of the reference signal .

The control unit 3 (FIG. 2) contains a multivibrator 11, a GSHI element 12, an AND 13 element, a first counter 14, a decoder 15, a first trigger 16, a one-shot 17, an element 2I-OR 18, a second trigger 19, the second and third counters 20. The correlator is built on the use of an algorithm for determining the probability of coincidence of the signs of the signals participating in the correlation (3); the mutually correlated function P (t) is determined by R (t) 2P (t) -1, (1) where P (t) - probability of coincidence of signs of correlated functions on the correlation interval at time t for the discrete representation of the expression signals (1) has the form: expression -1, Rh where Rh is the number of coincidences of samples of correlated functions on the correlation interval N is the correlation interval equal to the number of samples of the reference signal J K.T. Up to a constant factor of 2 / N The values of the mutual correlation function according to (2) can be produced using the equation r i Expression (3) is a mathematical description of the algorithm: the operation of the correlator. In accordance with it, in order to determine the value of Rk, it is necessary to calculate the number of coincidences of the signs of signal samples in the correlation interval and subtract half the number of samples of the reference signal from it. Each subsequent value of Rk + 1, Rk + 2 is calculated in the same way, after performing a shift of correlated signals in accordance with the well-known generalization of the calculation algorithm for a discrete representation of the signals. The device works as follows. In this case, three operations can be selected in the correlator: demultiplexing, computing (in accordance with expression (3), multiplexing). For the achievement of a given speed in the proposed correlator, the principle of conservation is used, i.e. .the combination of all three operations in time, during one clock cycle of the correlator. The correlator operation is controlled by the control signals from the outputs of control unit 3. The beginning of the clock cycle is the first synchronous pulse (SI) with synchronization input and the correlator of the next (k-ro) frame of input information, i.e., a set of 1) k-x single sampling of all n channels transmitted sequentially in a common multiplex channel. For the organization of pipeline processing, demultiplexer 1 and multiplexer 7 are made using buffer memory. In the demultiplexer, a buffer memory, made on the shift register as a converter of a sequential n-bit (by frame size) input into a parallel one, is necessary for storing the result of the demultiplexing until the calculation of the previous code of the input information . By the arrival of the first SI from the synchronization input of the next frame of information, the contents of demultiplexer 1 must be rewritten into d) registers 2. The contents of counters 5 are rewritten into the buffer memory of multiplexer 7 after the calculation operation ends, but not earlier than the multiplex operation of the previous tact results the work of the correlator and no later than the beginning of the next tact of work. In other words, the result of the calculation is rewritten from the counters 5 to the multiplexer 7 in the time interval between the input information frames. From the counters 5, simultaneously with the write pulse (from) the ID of the control unit 3. The content is copied to the multiplexer 7 under the action of the control signals VK1-VK (Fig. 2.3) from the output of the decoder 15 of the control unit 3. From the multiplexer, the result of the calculation goes to subtraction unit 8, performed on the adder, to the second inputs of which, from the converter 6 of the decimal code to binary, the binary additional code of the number - -. The decimal code converter 6 is binary by the operator specified N value in decimal code generates the binary code of the number N in control block 3 and the binary additional N code of the negative number X in the subtractor 8. Performing the operation of subtraction by expression (3) after multiplexing the samples eliminates the need to install n blocks of the virus, i.e. after the calzd counter 5, and allows one to get by with only one subtraction unit, which makes it possible to reduce the hardware costs for the implementation of the correlator. From the output of the subtractor, the information enters the registrar 9, which serves to present the digital information 6 in graphical form. Registers 2, reference signal register 10, RETAILED OR 4 elements, counters 5 participate in the third operation, operation calculation and calculation. The calculation of the correlation function starts at the moment when the reference signal is recorded in the reference signal register 10, the first N are stored input information frames. The operation of the correlator to the moment tg does not differ from the operation of the correlator after t (j except that from the control unit 3 a multiplexer 7 is given a signal prohibiting the output of information to the recorder 9. In this case, the reference signal register 10 is controlled by the same signals as registers 2. After the arrival of the nth clock pulse of the Cth frame of the input information, i.e., after the end of the demultiplexing operation, the OR element 12, the control unit 3 generates an OF (FIG. 3). By this pulse, the contents of the counters 2 rewritten into multiplexer 7 My registers 2 are shifted by one clock cycle, and the contents of the demultiplexer are recorded in the empty cells.After completing these procedures, registers 2 store the N-1 samples of the previous frames and the k-ro samples of the samples. The correlator is ready for the next cycle of operation. 3 controls in accordance with the code received from decimal code converter 6 to binary. It produces N clocking pulses (Fig. 3), which are used to poll registers 2 and 10 of the reference signal without erasing the information there. Readable

FIG. 1 of the registers 2 sampling signs arrive at the elements EXCLUSIVE OR 4, where they are compared with the sample sign of the reference signal. In the case of coincidence of characters, a pulse is generated, counted by the corresponding counter 5. At the end of the work cycle, the result of processing the k-ro frame will be stored in the counter 5, the frame distributed over the k + 1 channels in the demultiplexer 1, and from multiplexer 7 will be output to p ) The register is the result of processing the k-1 frame. The pop-mu si SI is formed from the IS and the next clock cycle of the correlator begins. In the proposed correlator, by using sign data to process signals instead of such arithmetic nodes as the order combiner, the mantis accumulator accumulating memory, the EXCLUSIVE OR elements and counters are used to simplify the correlator and reduce power consumption without reducing the accuracy of processing within resolution, dynamic range applied in seismic acquisition of recorders. .

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Claims (1)

A CORRELATOR comprising a multiplexer, a subtraction unit, a registrar whose output is the output of the correlator, a demultiplexer, the information and control inputs of which are respectively the first information input and synchronization input of the correlator, the outputs of the demultiplexer are connected to the information inputs of the corresponding L registers, a reference signal register, the information input of which is the second information input of the correlator, the decimal kOma to binary converter, the input of which is the input code for the length of the reference signal, a control unit containing a multivibrator, an AND element, a decoder, a single vibrator, an OR element, an II-OR element, first and second triggers, first, second and third counters, the discharge outputs of the first of which are connected to the corresponding inputs of the decoder, the output of the last discharge of which is through a one-shot, connected to the clock input of the second counter, a single input of the first trigger and the first input of the OR element, the output of which is connected to the first input of the 2I-IPI element, the second input of the OR element is connected with the second input of the 2AND-OR element, the clock input of the third counter and is connected to the output of the multivibrator, the control input of which is combined with the first input of the And element and connected to the single output of the first trigger, the zero input of which is connected to the output of the third counter, the second input of the And element is combined with the third input of the 2I-OR element and is connected to the single output of the second trigger, the zero output of which is connected to the fourth input of the 2I-IPI element, the single input of the second trigger is connected to the output of the second counter full-time inputs of which are combined with the installation inputs of the third counter, characterized in that, in order to simplify the correlator, h elements EXCLUSIVE OR and η counters are inserted into it, the inputs of which are connected to the outputs of the corresponding elements EXCLUSIVE OR, and the outputs are connected to the corresponding information inputs of the multiploxor, the control input of which is connected to the outputs of the decoder and one-shot of the control unit, the output of the multiplexer is connected to the first input of the subtraction unit, the second input of which is connected to the output of optional code SU „„ 1130874 a decimal to binary converter, the output of the subtraction block is connected to the information input of the recorder, the control input of which is combined with the clock input of the first counter of the control and control-. the demultiplexer input, the first inputs of the EXCLUSIVE OR elements are combined and connected to the outputs of the multivibrator and the AND element of the control unit, the second inputs of the EXCLUSIVE OR elements are connected to the outputs respectively. η registers, the control inputs of which are combined and connected to the output of the OR element of the control unit, the third input of the And element which is connected to the output of the reference signal register, the control input of which is connected to the output of the 2I-OR element of the control unit, the installation inputs of the third counter of which are connected to the output decimal to binary code direct code converter "