SU1120358A1 - Calculating device - Google Patents

Abstract

A COMPUTING DEVICE containing an adder, to the output of which a quad input is connected, the first input of the adder is the first information input of the device, a switch, the first input of which is the second information input of the device and connected to the phase inverter input, the output of which is connected to the second input of the switch, the output of which connected to the second input of the adder, a generator of clock pulses, the output of which is connected to the pack-. Equal to the input of the switch, the averaging unit, the output of which is the output of the device, is characterized in that, in order to increase the accuracy and enhance the functionality due to the division operation, the multiplying unit and the additional phase inverter and the switch are introduced, the first the input of the additional switch is the input of the device's signal-divider and is connected to the input of the additional phase inverter, the output of which is connected to the second input of the additional switch, output d which is connected to the third (L c input of the adder, the output of the quad is connected to the first input of the multiplier by the sign, the second input of which is connected to the output of the pulse generator, and its output through the averaging block is connected to the fourth input of the adder A switch is connected to the clock generator. 00

Description

The invention relates to computing and can be used in analog computing devices. A computing device for multiplying signals is known, which contains operational amplifiers, 5 large-scale resistors and quadrants. The drawback of the device is: low accuracy. The closest to the proposed device is intended to multiply the signals, containing the adder, to the output of which a quadr input is connected, the first input of the adder is the input of the first multiplier signal, the switch, the first input of which is the Input of the second multiplier signal is connected to the phase inverter input, the output of which is connected to the second input of the switch, whose output is Cp, with the second input of the adder, the output of the quadrant is connected to the input of the synchronous detector, the output of which is connected to The low pass filter stroke, whose code is the output of the device, controls the inputs of the switch and the synchronous detector and is connected to the output of the clock generator 2j. However, the known device is characterized by low accuracy due to the non-ideal characteristics of the quad and the instability of its transmission coefficient. In addition, the device does not allow dividing. The purpose of the invention is to improve the accuracy and the expansion of functional capabilities due to the performance of division. The goal is achieved by the fact that in the computing device containing the adder, to the output of which the quad input is connected, the first input of the adder is the first information input of the device, the switch, the first input of which is the second information input of the device and connected to the second input of the overspeed switch, the output of which is connected to the second input of the adder, a clock pulse generator, the output of which is connected to the control input of the switch, averaging unit J tim whose output is the output device 5 vped, enes multiplier by sign and an additional phase inverter and the switching ochatel; the first input of the additional switch; - the reader is the input of the device divider signal and the connections to the additional phase inverter input, the output of which is connected to the second input of the additional switch; the output of which is connected to the third input of the adder; the output of the quadr is connected to the first input of the smart shift unit on the sign, the second input of which is connected to the output of the clock generator, and its output through the averaging block is connected to the fourth input of the adder, the control input of the additional switch with Connected to the output of the clock pulse generator. FIG. 1 shows a functional diagram of the proposed computing device; in FIG. 2, a variant of the W of a unit multiplying by a sign. The device contains a quad 1, an adder 2, a switch 3, a phase inverter 4, an averaging block 5, an additional switch 6, an additional phase inverter 7, a generator of 8 clock pulses, the first information input (input of the first signal of the multiplier) 9, the second information input (input of the second signal -somnoshkitel) 10, input 11 of the signal-divider, output 12, block, 13 intelligently per sign. Block 13 in the case of use: -squad-square element with an even quadratic function, for example, on the basis of a multiplier with a Hall element, contains a phase inverter 14 and a switch 15 (FIG. 2). The device works as follows. From the input 9, the AC signal is continuously fed to the input of the adder 2. To the other input of the adder 2, through the switch 3, alternately, either the signal from input 10 or the signal is converted. called the phase inverter 4. To the third input of the adder 2, through the switch 6, the non-inverted and inverted voltage of the direct current is fed from the input 11. Thus, in the first cycle of operation, it is determined by the generator of 8 clock pulses, with poles of 3 and 6, corresponding to The other shown in FIG. 1, the input of quadrant 1 is the total voltage U (. K (x + yU + Z) K is the conversion coefficient of the adder 2, X, y-, the first and second signal multipliers, DO is the voltage of the divider signal, Z is constant component of the output voltage of the block 5 averaging. In the second cycle of operation (the position of the switches 3 and 6 opposite to the shown figure 1), the total voltage Uc2 (x-y + U + Z) is fed to the input of the square 1 13 in the steady-state average voltage value for two conversion cycles is equal to zero, since the mean values of quad Atoms of alternately squared signals by expressions (1) and (2) are equalized by changing the output SI of block 5. This is O 3) where K is the conversion factor of the quadrant 1. Substituting values (1) and (2) into expressions e ( 3) and produce averaging over the switching period, we get Z - CO yG (the bar above means averaging over the commutation period). Thus, the value of the output voltage does not depend on the instability of the transform coefficients. an adder 2 and a quadrant by which accuracy is increased. Moreover, if the first and second signal-factors and the signal-divider are independent, then multiply-divide by operation is performed. If the signal UQ is constant, or at X, then it is possible to carry out the operations of multiplication and squaring 1, respectively. If instead of a signal divider to serve the output. the signal is then converted to the effective value. So, in comparison with the known device, more accuracy and wider functional capabilities are provided.

1

R

14

2

G5 u

r

. J

} iOm generator 8

Claims (1)

A COMPUTER DEVICE containing an adder, to the output of which a quadrator input is connected, the first adder input is the first information input of the device, a switch, the first input of which is the second information input of the device and connected to the input of the phase inverter, the output of which is connected to the second input of the switch, the output of which is connected to the second input of the adder, a clock generator, the output of which is connected to the control input of the switch, an averaging unit, the output of which is the output of the device property, characterized in that, in order to improve the accuracy and expand the functionality due to the division operation, a multiplier by a sign and additional phase inverter and a switch are introduced into it, and the first input of the additional switch is the input of the signal divider of the device and connected to the input of the additional phase inverter, the output of which is connected to the second input of the additional switch, the output of which is connected to the third input of the adder, the output of the quadrator is connected to the first input of the block multiplication by a sign, the second input of which is connected to the output of the clock generator, and its output through the averaging unit is connected to the fourth input of the adder, the control input of the additional switch is connected to the output of the clock generator. „„ SU „„ 1120358