RU1797161C - Converter from shaft rotation angle to code - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used to connect analog information sources with a digital computing device. In order to increase the accuracy by averaging the selected number of instantaneous angle measurements with the possibility of switching through the maximum value of the codes into a shaft rotation angle converter into a code containing a pulse generator, a first frequency divider, a power supply, a phase shifter, a sector selector, an analog-to-digital converter, a functional block code conversion, a first adder, a first register, a second frequency divider, a running bus, a synchronization element, a pulse shaper, a second adder, a second register; decoder, four AND elements, two triggers and an OR element. In the first adder, instantaneous values of the displacement code are generated in the form of the difference between the phase and reference sawtooth codes. The second adder and the second register form an accumulative adder to add up the selected number of instantaneous angle values of the first adder. The decoder, AND, OR elements, triggers and code bus are designed to eliminate the error of summing codes when passing through the maximum value in the averaging cycle. 2 ill.

Description

The invention relates to the field of automation and computer technology and can be used to connect analog information sources with a digital computing device.

The aim of the invention is to increase accuracy by averaging the selected number of instantaneous angle measurements with the ability to go over the maximum value of the codes.

In FIG. 1 is a structural diagram of a converter; in FIG. 2 - cyclogram of his work.

The converter contains a pulse generator 1, divide l.) 2 and 3 frequencies, power supply unit 4, phase shifter 5, synchronization element 6, 7 sectors selector, analog-to-digital converter (ADC) 8, functional code conversion unit 9, adders 10 and 11 Registers 12 and 13, pulse generator 141, decoder 15, I-elements 16-19, triggers 20 and 21, OR element 22, code bus 23. Sector selector 7 contains a block of 24 rectifiers, a block of 25 comparators, a register 26, an encoder 27. switch 28.

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The device operates as follows.

Generator 1 generates high-frequency pulses with a frequency. At the outputs of the dividers 2 and 3, sawtooth-shaped codes are generated in function of time with frequency. with a measurement resolution equal to the period of the oscillator 1. From the output code of the divider 2, block 4 generates multiphase reference harmonic signals (for example, sine and cosine) with a frequency f0 of the supply of phase shifter 5. As a phase shifter 5, a sine-cosine rotary transformer E can be used (SCRT ) or selsyn in the rotating field mode with a negative sequence filter to compensate for the technological errors of the phase shifter. The phase shifter 5 converts the multiphase reference harmonic signals of block 4 into phase-modulated harmonic signals (for example, sine and cosine) and displacement functions.

The frequency divider 3 operates continuously, as does the divider 2. At a zero value and, for example, with a positive gradient of one of the signals of block 4, element 6 generates a pulse synchronized with one of the edges of the pulses of generator 1. The output pulse of element 6 is supplied to the installation input of the divider 3 and enters into it from the parallel loading bus 23 an initial code whose value is selected so that in the initial state of the moving object the output code of the converter is zero. The reference ramp code of the divider 3 is shown in FIG. 2a, and in the general case it is phase shifted with respect to the output code of the divider 2. The transmission coefficients of the dividers 2 and 3 are chosen to be the same 2K. The output signals of the phase shifter 5, the movable part of which moves at a speed Q, are shown in FIG. 26,

In the selector 7, the sector number of the phase-modulated signals of the phase shifter 5 is determined using blocks 24-28. The rectifiers of the block 24 detect the output signals of the phase shifter 5. The comparators of the block 25 generate rectangular signals from the sine signal (Fig. 2c), the cosine signal (Fig. . 2d) of the phase shifter 5 and from the output signals of block 24 (Fig. 2e).

On one of the pulse edges of the generator 1, the output code of the comparators of block 25 is fixed in the register 26. The one-variable output code of the register 26 is converted in the decoder 27 to an arithmetic code. The lower bit of the register code 26 controls the operation of the switch 28 so that the smaller of the output voltages of the block 24 is fed to the information input of the ADC 8, and the larger modulo -

reference input of the ADC 8. In the ADC 8, a code is generated for the ratio of the smaller modulated phase shifter signal 5 to the larger inside each sector. In block 9 by inverse trigonometric

0 code conversion, the ADC 8 output code is converted to a linear argument code (for example, by generating an arc tangent code) and in even sectors, with a single value of the least significant bit of the code

5, encoder 27 is inverted. The output code of block 9 is shown in FIG. 2g A phase sawtooth code (Fig. 2h) with a period of the output signal of the phase shifter 5 is generated from the output code of the encoder 27

0 (high order) and block output code

9 (low order).

In the adder 10, instantaneous values of the displacement code (FIG. 2i) are generated in the form of a difference of a phase sawtooth code

5 (Fig. 2h) and a reference sawtooth code of the divider 3 (Fig. 2). With a resolution of converting the amplitude of the output signals of the phase shifter 5 to a code corresponding to K bits, the change of information in the adder 10 occurs in each period of the generator 1.

However, the phase information of the adder

10 is unstable due to the influence of random pickups. The adder 11 and the register 12 forms

5 accumulating adder to summarize the selected number of instantaneous values of the angle of the adder 10. However, the usual summation is unacceptable due to a spasmodic change in the output code of the adder 10 when crossing the border

pole division, To exclude (errors in the summation of codes, the sum of the torus 10 is a combination

elements 15-22.

5, in the decoder 15, the state of the two high-order bits of each value of the output code of the adder 10 is analyzed. At the zero state of these bits, the output signal of the decoder 15 passes through the open element 16 and sets trigger 1 to 20. Element 17 And closes, and element 18 opens. In this state of the decoder 15, as well as increasing the code sum. Matter 10 (Status of its senior ranks

5 is 01) from the outputs of elements 18 and 22, zero signals are fed to the inputs of the higher bits of the first group of inputs of the adder 11. On the edge of the pulse from the inverse output of the generator 1, the output code of the adder 11 is written in register 12, which is the sum of the previous codes in register 12, with the current value of the code of the adder 10. With a period corresponding to the selected number of summed code values, a pulse edge is output from the output of the divider 2, according to which the output code of the register 12 is written to the register 13. According to the same Ronto shaper 14 is generated in a narrow, slightly delayed pulse on which are reset to 0 flip-flops 20, 21 and the register 12. The new cycle begins averaging and generating output code with a period equal to the period of the selected intermediate output) frequency divider 2 thou.

If, the output code of adder 10 decreases and in one averaging cycle crosses the boundary of the pole division of phase shifter 5 (high-order code changes from state 00 to state 11), for each value of the code of the TO adder with high-order bits 11, the signal from the second the output of the decoder 15 passes through the elements 18 and 22 and in the form of a single signal is fed to the input of the higher bits of the first group of inputs of the adder 11. As a result, the error of summing the codes when crossing the boundary of the pole division of the phase shifter 5 is eliminated.

When crossing the boundary of the pole division of the phase shifter 5 in the direction of increasing codes (the high order code of adder 10 changes from state 11 to state 00), trigger 21 is first set to 1 by the signal from the second output of decoder 15. Then, for each value of adder code 10 with high-order bits 00, the signal from the first output of the decoder 15 passes through elements 19 and 22 and enters the input of the lowest of the high-order bits of the first group of inputs of adder 11, which also eliminates the error of summing codes. In the absence of averaging of transitions across the pole pressure of the phase shifter 5 from the outputs of elements 18 and 22, zero signals are received at the corresponding inputs of adder 11.

The measurement accuracy of the transducer compared to the prototype increases in Vnpas, where n is the number of averaged instantaneous angle values in one measurement cycle. The converter allows a change in the angle of rotation in the measurement cycle (taking into account all the errors of the converter) not more than a quarter of the pole division of the phase shifter 5. An increase in the allowable change in the angle is impractical due to an increase in the dynamic error. The duration of the measurement cycle is determined by the output number of the divider 2, connected to the input of the shaper 14 and the C-input of the register 13, and can quickly change during operation depending on the requirements of the converter.

Claims (1)

SUMMARY OF THE INVENTION A converter of a shaft rotation angle into a code comprising a pulse generator, a first frequency divider, a power supply, a phase shifter, a sector selector, the analog outputs of which are connected to the inputs of the analog-to-digital converter, the outputs of the analog-to-digital converter are connected to the group of inputs of the block functional code conversion, the outputs of which and the digital outputs of the sector selector are connected respectively to the lower and upper bits of one group of inputs of the first sum a torus, a first register, characterized in that, in order to increase the accuracy of the converter, a second frequency divider, a code bus, a synchronization element, a pulse shaper, a second adder, a second register, a decoder / four AND elements, two triggers and an OR element, etc. are introduced into it. my output of the pulse generator is connected to the counting input of the second frequency divider and to the synchronization inputs of the sector selector and synchronization element, the information input of which is connected to one of the outputs of the power supply, and the output is connected to the installation the input of the second frequency divider, the information inputs of which are connected to the code bus, and the outputs are connected to another group of inputs of the first adder, the outputs of which are connected to the low-order bits of the first group of inputs of the second adder, the outputs of the two high-order bits of the first adder are connected to the inputs of the decoder, the first the decoder output is connected to the first inputs of the first and second elements And, the second decoder output is connected to the first inputs of the third and fourth elements And, the outputs of the first and third elements And s to one input, respectively, of the first and third triggers, the direct outputs of which are connected respectively to the second inputs of the fourth and second elements AND, and the inverse outputs are connected to the second inputs of the third and first elements AND, the outputs of the second and fourth elements AND through the OR element are connected to the input of the least significant bit of the first group of inputs of the second adder, the output of the fourth element And is connected to the inputs of the remaining high bits of the first group of inputs of the second adder, the outputs of the second adder are connected to the information inputs of the second register, the outputs of which are connected to  / X / x / xv ) W LLLLLLL / LLLLLLLLLA L / LLLALLALLALLA the second group of inputs of the second adder and to the information inputs of the first register, the outputs of which are the outputs of the converter, one of the outputs of the first frequency divider is connected to the control input of the first register and through the pulse shaper to other inputs of the first and second triggers and to the reset input of the second register, the control input of which is connected to the inverse output of the pulse generator, one of the digital outputs of the sector selector is connected to one input of the functional code conversion unit.