SU1117822A1 - Method of adjusting static frequency converter - Google Patents

Abstract

A DEVICE FOR CONTROLLING A STATIC FREQUENCY CONVERTER containing two inverters connected to a common load, a master oscillator, two control pulse shapers, the first control pulse shaper intended to be connected to the control input of the first inverter, the adjustable delay unit whose first input is intended for connections via the voltage sensor with the output of the first and second inverters, and the output through the element I, the IL element and the second pulse driver is designed to Unification with the control input of the second inverter, characterized in that, in order to expand the functionality and increase the reliability of the device, W frequency divider, OR-NOT element, AND-NOT element are entered into it, the output of the master oscillator is connected to the input of the frequency divider, the first output of which is connected through the first input of the element OR-NOT to the first input of the element OR and through the first input of the element AND-NOT to the first input of the element AND and to the input of the first driver of the controlled pulses, the second output of the frequency divider It is connected to the second inputs of the WLNE element, the NAND element and the adjustable delay light.

Description

 one

The invention relates to electrical engineering and can be used in the development of static frequency converters for individual and centralized power supply for induction heating of metals, etc.

Adjustable delay devices are known with separate functional elements that are used for phase control of thyristor frequency converters, in particular, rectifiers l 2J.

Closest to the invention, the technical entity is a device for controlling a static frequency converter comprising two inverters, the outputs of which are combined and connected to the load and the input of a voltage sensor, the output of which is connected to one of the inputs of the adjustable delay unit, to the other input of the adjustable unit delays are connected to the output of the master oscillator and the input of a block of fixed delay, the output of which is connected to the input of the first inverter through a pulse shaper, a fixed delay whose input is connected to the output of the master oscillator, an AND element, one of whose inputs is connected to the output of an adjustable delay unit, another input to the output of a fixed delay unit, an OR element, one input of which is connected to the output of the AND element, another input to the output of the additional fixed delay unit, the output of the -OR element, is connected to the control input of the second inverter sj via a pulse shaper.

A disadvantage of the known device is that the adjustment process requires a large number of adjustment elements, which significantly complicates the circuit.

In addition, the use of fixed-delay units reduces the functionality of the FHC, its reliability of operation, therefore, narrowing down.

The aim of the invention is to enhance the functionality and increase reliability.

This goal is achieved by the fact that the device for controlling a static frequency converter, co222

holding two inverters connected to a common load, master oscillator, two control pulse shapers, the first control pulse shaper is designed to be connected to the control input of the first inverter, an adjustable delay unit, the first input of which is intended to be connected

through the voltage sensor with the output of the first and second inverters, and the output through the AND element, the OR element and the second pulse shaper are designed to connect to the control input of the second inverter, a frequency divider, the OR-NOT element, the AND-NOT element, and the output | The oscillator is connected to the input of a frequency divider, the first output of which is connected through the first input of the OR element to the first input of the OR element and through the first input of the NAND element to the first input of the AND element and to the input of the first driver of control pulses A swarm output of the frequency divider is connected to the second inputs of an OR-NOT element, an AND-NOT element, and an adjustable delay unit.

FIG. 1 shows a functional diagram of the device; on Fig.2 time diagrams of his work.

The device contains two inverters 1 and 2, load 3, voltage sensor 4, adjustable delay block 5, frequency divider 6, element AND-NE 7, element OR-NOT 8, master oscillator 9, element 10, element OR 11, drivers 12 and 13 control pulses.

The device works as follows.

The master oscillator 9 generates square-shaped pulses with a period of 0.25 T, where T is the period of the output frequency 41 (Fig. 2a). These pulses are fed to a frequency divider 6, having two outputs i and 2f (Fig. 26, c). At output 21, pulses with a period of 0.5 T follow, and at output i, with a period of following T. These pulses are fed to the inputs of the AND-NE 7 element, the OR-NOT 8 element and to one of the inputs

An adjustable delay unit 5, at the output of which the following pulse commands are formed (Fig. 2d, e).

3, 11

As a result, the condition is always automatically satisfied.

t.

-g

  miM - T.

The control signal at the output of the voltage sensor 4 varies depending on the load value of the converter. At various values of the magnitude of this signal, the pulse duration reg (fig, 2d) generated by the variable delay unit 5 can vary from 0 to T, which can lead to loss of control pulses and the inverter thyristors in the transition mode for overvoltages, therefore the pert command. {Fig. 2d) is converted into a tprp command (Fig. 2g) by successively adding commands, t per game, (Fig. 2d, e, e), carried out by And 10 elements and

78224

OR 11 so that the duration of the COGH pulse (Fig. 2g) is within Cp, Oo, p (), i.e. the change in its duration did not exceed 0.5 T. Then the impulse commands; uk opt (fig, 2g, g) are fed to the formers 12 and 13 of control pulses, which form the commands for phase control of inverters 1 and 2,

The operation of the limiting range circuit for controlling the phase of the inverter control pulses does not depend on the operating frequency of the FH, since at any frequency the change range of the command otp (Fig. 2g) is determined by

Respectively and

ness h /

stumps

max

..the phase shift between the control pulses of the inverters will never go beyond the limits of 0-180 el. grades, which is necessary for the stable operation of the FH,

Nmp

/

s b

2f

f

g imp

mtuk.

 NML.

reg.

e "l

mirt

F, Yaml

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Claims (1)

DEVICE FOR MANAGING A STATIC FREQUENCY CONVERTER, comprising two inverters connected to a common load, a master oscillator, two control pulse shapers, the first control pulse shaper designed to connect to the control input of the first inverter, an adjustable delay unit, the first input of which is intended for connection through a voltage sensor with the output of the first and second inverters, and the output through the element Y, the OR element and the second pulse shaper is designed to connect with a control input of the second inverter, characterized in that, in order to expand the functionality and improve the reliability of the device, a frequency divider, an OR-NOT element, an AND-NOT element are introduced into it, and the output of the master oscillator is connected to the input of the frequency divider, the first output which is connected through the first input of the OR element NOT to the first input of the OR element and through the first input of the AND element NOT to the first input of the AND element and to the input of the first driver of control pulses, the second output of the frequency divider is connected to the second moves element NOR, NAND and adjustable delay unit. SU „„ 1117822