SU1115215A1 - Device for delaying pulses - Google Patents

Abstract

A DEVICE FOR DELAYING PULSES containing the first pulse counter, the inverse outputs of which are connected through the rewriting unit alternately to the write inputs of the second counter HMnvribcoB, the first delay element whose input is connected to the converting input of the second pulse counter and the input bus, and the output to the enable input the rewriting unit and the input of the second delay element, the output of which is connected to the zeroing input of the first pulse counter, the clock pulse generator and the AND elements, the inputs of each of which are connected to corresponding outputs of the second pulse counter, and outputs with corresponding output buses, differing from the fact that, in order to increase the stability of the advanced lead interval, a pulse driver, a frequency multiplier, an additional counter, a valve block and a controlled delay device are inputted to it, the pulse driver is connected to the input bus, and the output through the clock pulse generator is connected to the counting input of the first pulse counter, which connects the additional input (3 meters and the input controlled S delay devices, another output of the clock generator through a frequency multiplier is connected to the counting input of an additional counter, the outputs of which through the valve block are connected in parallel with the inputs of the controlled delay device, the output connected to the counting input of the second pulse counter, and the output of the first delay element connected to the enable input of the valve block.

Description

I The invention relates to a pulse technique and is designed to use 3 synchronization devices to obtain a sequence of HNI pulses J leading by a given time period; one sequence of impulses A device is known for delaying impulses containing a 1 counterpulse generator, two counters of code comparison circuits, remembering its structure, the first and second triggers, the three AND elements, the delay generator SP. In this device, pulses are delayed, delayed by time T - t; where T is the period of the following input pulses; - a constant value determined by the frequency of the clock pulses and the number of de-corrugating the third element I, and not depending on the frequency of the input pulses, More than 3, it is not difficult to get This is the instability of the pulse advance time during the variation of the period C3: units; 1i input pulses, Lime.) device d, -:,; -: holding the pulses 5 co; o; , em ment co: padeiin ..:; p5g- s-- --k:;: ;; Ka, 5Lr. СЧЦТЧНКс .. /. l; ; .ii-t of my key, trigger, sncMeiiTC g. Dineni, multi-input-: 1x and. move; of the left elements coincide 1n; The disadvantage of the following: o yo, oyg: -va is that 5 that irk K3M "; ie: vMr-fiepCode following enter) x them; t y. ..with:; arena ahead of rust; --pchiu isii;:;::; the next input Miv; nyjin ;.: a magnitude inappropriately nnay, The closest to the invention to the technical essence of YaB1E is a device for loading and holding pulses, consisting of a clock VIM pulse generator, two counters. Griggra, the first and second And elements, two elements of the dead skin, as well as from the And elements and the rewriting block. In this device, the output i of the clock pulse generator is connected to the first input of the first element I, the second input of which is connected to the trigger output, and the output to the input of both counters, the input of the first delay element is connected to the input of the device, unit E1 in the second trigger to the reset input second count I J chick, the inputs of the second element And state-HeFibi with the corresponding bits in the second counter, 1 output of the second delay element coejT, Nnen with zero input; oh trigger and the reset input of the first counter, Bfc output of the first element delays with the input of the second element of the rear ;; The inputs of the second counter, the inverse output of the last bit of the first counter, are connected to the input of the first lorn element I, the output of each C of the cells And are connected to the corresponding: :::: t; vHJiuiiMir by the serial outputs, -torog: h: П1каГ3 ,. 11; viOC;.: Gko1- known devices: tva ppggtsa 1izka stability of the FG {Induced interval of advancing g; curing the period of the following pulses. The purpose of the invention is noBbiiieHVi: - I formed the bHTSpiTJi formed by HHrepi a.opore1 ;; s: 11i with the change; ui: 1C-z; -od ;: .iU.:.: i; o) -i4KH in, ni-iiiy:; ь Of Of: l. (;. c-,; o ::: gig STS: iOi that in the mean- ...: with,:; e e ncpBhjM counter::; -y,;:;,;.,:, Ul; U; pCHhie OUTPUTS OF KOTORCHGO: .- re :: highlight The record is connected i rii: yii; at the inputs of the record of the second midpoint ;; T; :: kg- lyynrjobcoB 5 the first element of the posterior Q: -, HH: this; NHO / NOA BUS, 8 OUTPUT at razrav110 ;, or 1 input unit of the reloading unit and gukodou; the second element: s; upd, K (the second is connected to the updated; -th input of the first impulse counter, the generator of clock pulses and i elements And, the entrances are each of which They are connected with the corresponding outputs of the second impulse counter, and the outputs with the corresponding 1), they have entered the forms for the Bychod 15 tires: spruce pulp, complementary with h: et h and k. b l in f a t and a controllable delay device and a multiplier with the frequency of which the input of the pulse former is connected to the input bus J and step through the generator tag: - combo pulses with counting input: the mind of the first pulse counter; : -: and the input of the controlled delay device, another output of the generator VA;

31

Pulses are connected via a frequency multiplier to the counting input of an additional counter, the outputs through a valve block are connected in series with the inputs of a controlled delay device connected by an output to the counting input of the second pulse counter, and the code of the first delay element is also connected to the enable input of the valve block,

Figure 1 shows a block diagram of a device for delaying pulses, figures 2 and 3 are temporary d; diagrams illustrating the operation of the device.

The device contains a pulse former 1, a generator of 2 clock pulses, a frequency multiplier 3, a pulse counter 4, a rewriter unit 5, a pulse counter 6, element 7, the first 8 and second 9 delay elements, an additional counter 10 pulses, a valve block 11 and a controlled device 12 delays.

When this shaper 1; generator 2 and counter 4 are connected in series, the inverted outputs of counter 4 through rewriting block 5 are directly connected to the inputs of counter 6, the counting input of which is connected to the output of controllable delay device 12, another output of generator 1 through frequency multiplier 3 is connected to counting input of counter 10 the outputs of which through the valve block are connected in parallel to the inputs of the controlled delay device 12, the input of which is connected to the insulating input of the counter 10 and connected to the output of the generator 2, the inserting input of the counter 6 connecting with the input bus of the device and through the first delay element with the control input of the rewriting unit 5 and the enabling input of the valve unit; which, via the second delay element, are connected to the zeroing input of the striker 4, the inputs of the And 7 elements are connected to the corresponding outputs of the counter 6, and the outputs to the output buses of the device.

The operation of the device is as follows.

Using a pulse generator 1, the input sequence of pulses U (Fig. 2a and Za) is converted into a sequence of pulses.

154

standard amplitude and duration u2Dfig.2b), providing phase generator of 2 clock pulses, which forms a sequence of highly stable pulses of some fixed frequency. The generator 2 can be performed, for example, in the form of a series-connected auto-oscillator, whose frequency is stabilized by quartz, and a pulse former that converts the harmonic oscillations of the ultrasound (Fig. 2c) frequency fte into a sequence of pulses (Fig. 2d) of the same frequency. The autogenerator is phased by a pulse applied to the input of the generator. At the moment of the appearance of such a pulse, a certain value of the initial phase of the oscillations of the generator is established. In addition, the input signal U is set to the zero position of the pulse counter 6. Delayed relative to the pulse Uf at time Tj / pulse Ug (FIG. 2d) from the output of delay element 8, the contents of counter 4 are transferred to counter 6, and pulse IJi (FIG. 2c and Sv) from the output of delay element 9 delayed relative to the output pulse element 8, at time 32 3, counter 4 is zeroed. The latter counts during the period following the input signal the pulses of the clock pulse generator, i.e. In fact, it measures the follow-up period of the input pulses. With the arrival of each successive impulse of the input sequence, code N, proportional to the period of impulses of the input sequence, from counter 4 through rewriting unit 5 is rewritten in reverse code into counter 6.

The pulses Ug from the other output of the generator 2 through the multiplier 3 frequencies (Fig. 3d) are sent to the counting input of the counter 10, which is reset to zero by each pulse from the first output of the generator 2. As a result, to the arrival of the next pulse of the input sequence, the code H is generated in the counter 10, proportional to the required delay of the signal (equal pulse advance time (j pulse U, which, with the arrival of the next pulse of the input sequence through valve block 11 51), is copied to the delay device 12. The second input of the counter 6 from the output of the device 12 receives pulses delayed by a given value (Fig. 2g of the generator 2. With such a delay, it will appear that one of the delayed pulses Ug (at the time in Fig. Ze) necessarily coincides with next impulse U ato means that at the outputs of elements And 7 output impulses} (Fig. 3) are ahead of the impulses of the sequence and, by an integer number of periods, and this advance is the same from period to period. Elements 7 are designed to select signals at times when the code recorded in the pulse counter 6 takes a certain value of Ho, which determines the required time for the output pulse ahead of the input signal. The required value of the code K, set 5 yts by connecting the corresponding Ezyhodon counter 6 pulses to the outputs of the elements And 7. with; the arrival of the next input pulse and, the cycle of operation of the device is repeated. When changing the frequency of the input pulses, it takes one period to set a previously set lead time with a new value of period T. The accuracy of setting the lead time to for the proposed device is determined by the uncertainty of the setting of the setpoint in the controlled device of the setpoint and does not exceed the frequency period of the multiplier. The unstabilization of the advance time of the device is due to the instability of the driver — the pulses and the generator of taksiTOBiX pulses. These instabilities are extremely small and for most cases are in the order of 10 to 10

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Claims (1)

A device for delaying pulses, containing the first pulse counter, whose inverse outputs are connected through the overwrite unit bitwise to the recording inputs of the second counter of img.-pits, the first delay element, the input of which is connected to the zeroing input of the second pulse counter and the input bus, and the output to the enable the input of the rewriting unit and the input of the second delay element, the output of which is connected to the zeroing input of the first pulse counter, a clock pulse generator and r AND elements, the inputs of each of which are connected to corresponding outputs of the second pulse counter, and the outputs with corresponding output buses, characterized in that, in order to increase the stability of the formed advance interval, a pulse shaper, a frequency multiplier, an additional counter, a valve block and a controlled delay device are introduced into it, and the shaper input pulses are connected to the input bus, and the output through the clock generator is with the counting input of the first pulse counter, resetting the input of the additional counter and the input of the controlled delay device, another output of the clock generator through the frequency multiplier is connected to the counting input of the additional counter, the outputs of which through the valve block are connected bitwise to the inputs of the controlled delay device, the output connected to the counting input of the second pulse counter, and the output of the first delay element is connected to the enable input of the block gates. SU. „, 1115215 W 521 5