SU1111161A1 - Firmware control unit - Google Patents

Abstract

FIRMWARE CONTROL MICROPROGRAMME., Containing a microinstructor memory block, address register, microinstruction register, clock generator, condition control unit, first and second counters and an encoder containing an input decoder, n elements OR (and 1,2, ...) and (vi-1) / 2 l decoders, with the first group of inputs of the condition control block connected to the output group of the microinstructions register address code, the group of information inputs of which are connected to the first group of information outputs of the microinstruction memory block; which is connected to the group of information outputs of the address register, the group of information inputs of which is connected to the group of outputs of the condition control unit, the second group of inputs of which is the group of inputs of the logic conditions code of the device, the output group of the operation codes of the microcommand register is the output group of the operations code of the device, the enable input of the register of microinstructions is connected to the enable inputs of the recording of the first and second counters and the output of the loan of the second counter whose counting input is connected to , the counting input of the first estimator, the sync input of the microinstructions register, the synchronization input of the address register and the output of the clock pulse generator, the setup input in the O. register address is the input of the initial setup of the device and connected to the setup input of the second counter, the group pa informational inputs of which connected to the second group of information outputs of the microinstructions memory block, the third group of information outputs of which is connected to the group V) information inputs of the first counter, information group the ion outputs of which are connected to the inputs (and -1) / 2 decoders, the group of outputs of the micro-command register control code is connected with the group of inputs of the input decoder, the outputs of the i-th decoder (, 2, ..., (and-1) / 2) respectively, connected to the i-th inputs of the OR elements, whose outputs are the control outputs of the device; the strobe input of the th-th decoder is connected to the th-th output; the input decoder, which is in order to simplify the device, the output of the control bits of the formation of control signals of the register of microsomers j is connected to the input of the control sche direction, that the first counter.

Description

1 11 The invention relates to the field of automation and computer technology, in particular to firmware control devices, and can be used in digital computing systems, as well as terminal equipment. A firmware control device containing a microinstructions memory block, a microinstructions register, an address register, a condition checker, a group of elements AND, a lock register, a pulse generator, and an element til is known. The disadvantage of this device is the limited set of combinations of micro-orders made in each individual micro-command. The closest in technical essence to the present invention is a firmware control device comprising a microcommand memory block, an address register, a microcontroller register, a clock pulse generator, a condition monitoring unit, first and second counters, and an encoder, the first group of condition control inputs connected to the group of outputs of the code of the address of the microinstruction register, the group of information inputs of which is connected to the first group of information outputs of the microinstructions memory block, the group of address inputs of which are connected There is no reference to the group of information outputs of the address register, the group of information inputs of which are connected to rpyn of the outputs of the condition control unit, the second group of inputs of which are connected to the group of inputs of the logical conditions code of the device, the output group of the opcode of the microcommand register, and the group the encoder outputs are connected to the device control output group, the first group of encoder inputs are connected to the output group of the micro-command register control code, the input is enabled. The NIN records of which are connected to the resolution inputs of the records of the first and second counters and with the output of the loan of the second counter, the counting input of which is connected to the counting input of the first counter, with the synchronous input of the micro-command register, with the output of the clock generator and the synchronous input of the address register and the input installation to zero which is connected to the input of the initial installation of the device and to the installation input to zero of the second counter, the group of information inputs of which is connected to the second group of information outputs of the block the memory of microinstructions, the third group of information outputs of which is connected to the group of information inputs of the first counter, the group of information outputs of which is connected to the second group of inputs of the encoder. The encoder contains the input descrambler n elements OR (, 2, ...) and (p-1), decoders, and the outputs of the j-ro decoder (, 2, ... (-1)) are connected respectively to the j-th inputs of the IDN elements whose vpdsody are connected respectively to the outputs of the encoder's output group, a group of inputs (and-1) (the decoders are connected to the second group of inputs of the encoder, the control input j-ro of the decoder is connected to the JM ropspe of the input decoder, the group of inputs of which is connected to the first group inputs of the encoder 2. The disadvantage of this device is its complexity, due to Enna, large equipment of the encoder. The purpose of the invention is to simplify the device. The goal is achieved by the fact that in the microprogrammed control device containing the microcommand memory block, the address register, the microinstruction register, the clock generator, the condition monitoring unit, the first and second counters and the encoder, containing the input decoder, m-elements OR (, 2, ...) and (and -1) i / 2 decoders, with the first group of inputs of the condition control block connected to the output group of the microinders register address code code, the information input group which is connected to the first group of information outputs of the microinstructions memory block, the group of addresses of the inputs of which is connected to the group of information outputs of the address register, the group of information inputs of which are connected to a group of outputs of a condition monitoring unit, the second group of inputs of which is a group of inputs of the logical conditions code of a device, a group of outputs of an operation code of a microcommand register is a group of outputs of an operation code of a device, the enable input of a register of microcommands is connected to an enable input

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records of the first and second counters and the loan output of the second counter, the counting input of which is connected to the counting input of the first counter, the synchronization input of the register of microinstructions, the synchronization input of the address register and the generator output. clock pulses, the installation input in the O register of the address is the input of the initial installation of the device and connected to the installation input in the O second counter, the group of information inputs of which are connected to the second group of information outputs of the microcommand memory block, the third group of information outputs of which are connected to the group of information inputs the first counter, the group of information outputs of which is connected to the inputs (p-1) / 2 decoders, the group of codes of the micro-command register control code is connected to the group of inputs output decoder, the outputs of the i-ro decoder (, 2, ..., (10-1) 1/2) are connected respectively to the i-th inputs tq of the OR elements, the outputs of which are the control outputs of the device, the gate input i-ro The decoder is connected to the i-th output of the input decoder. The output of the control control signal generation bit of the micro-register register is connected to the control input of the counting direction of the first counter.

FIG. 1 shows a diagram of the device; in fig. 2 is a diagram of the control unit of the words; in fig. 3 - encoder scheme; in fig. 4 - time diagram of the device.

The microprogram control device contains a block of 1 memory of micro-instructions, a register of 2 micro-instructions, a register of 3 addresses, a block 4 of condition monitoring, a generator of 5 pulses, the first 6 and second 7 counters, an encoder 8, a group of outputs 9 and a group of inputs 10 of the device, input 11 initial installation, a group of outputs 12 devices.

The condition control unit 4 (FIG. 2) contains groups of elements 13 AND and 14 OR.

The encoder 8 (Fig. 3) contains (input decoder 15, a group of decoders 16 and a group of elements 17 OR

FIG. 4 marked: 18 - the signal of the initial installation at the input 11 of the device; 19 - pulses at the output of the generator 5 pulses; 20 - signal of the output at the control output of the counter 14

ka 7; 21, 22, 23, 24 - signals on the fourth, third, first and second outputs of the encoder 8, respectively.

The firmware control device operates as follows. To bring the device into the initial state, a signal 18 is sent to its input 11, by which the register 3 addresses and the counter 7 are set to 0 s in O. At the zero address from the micro-instruction memory block 1, the initial micro-instruction is selected and fed to the information inputs of the micro-command register 2. At the exit of the loan, the counter 7 generates a signal 20 of the loan and enters the inputs of the resolution of the recording of the register of 2 microcommands and counters 6 and 7. By impulse 19, the corresponding parts of the microcommand are entered

0 in the register 2 microinstructions and counters 6 and 7.

Each microinstruction consists of a track of parts — address, operational, and control.

5 In the address part of the microcommand, in addition to the code by which the address of the next microcommand is determined, contains one bit, the value of which determines the type of transition (conditional

0 or unconditional) to the next microinstruction. The address part of the micr command comes from the group of outputs of the code of the address of register 2 microcommands to the first group of inputs of block 4 of the control, conditions.

The microcommand operation part contains an operation code that is executed by the operating circuits controlled by the given firmware manager.

Q device. The operational part of the microcommand comes from the group of outputs of the operation code of register 2 microcommands to the group of outputs 9 of the device.

In the control part of microcommand

5 sets information about the combination and the number of micro orders that drop. c when executing this microcommand.

For a clearer understanding of

We look at the further operation of the device for the case when the maximum number of micro-orders issued in one micro-command is, for example, four .:

A full set of combinations of four

rex micro-orders are presented in table. 1. Micro orders are designated by serial numbers - 1 - 4. Out of 1t-abl. As can be seen from Fig. 1, the total number of comic character for combinations of micro-orders of any of the eight sections of the enhanced zone of Table 1. Thus, a set of combinations of micro-orders, presented in Table. 2 is functionally complete for the operation of the device in this case. In accordance with the table. 2, the fields are distributed in the control part of the microcommand and the encoder 8 is built. The control part of the microcommand includes three fields and an account direction control bit. In the first field, the row number is specified in accordance with Table. 2-. The line number is entered in the register of 2 micro-commands and comes from its control outputs to the inputs of the encoder 8. In the second field of the control part of the micro-command, the column number is set according to the table. 2. The column number is entered into counter 6 and is fed from its outputs to the inputs of the encoder 8. In the third field, the number of micro-orders issued in the micro-command is specified. This field is entered into the counter 7. The control bit of the counting direction is fed to the corresponding input of the counter 6. The input decoder 15 is the decryptor of the strings in accordance with the table. 2. Its inputs receive signals from the control outputs of the register 2 mikr6sh) mand. Each of the group of decoders 16 corresponds to the row in the table. 2; the first is null, the second is first, etc. The connection of the outputs of the decoder's .16 code to the inputs of the group of elements 17 OR corresponds to the location of the micro orders in the corresponding row. For example, the first to fourth outputs of the first decoder are connected respectively to the inputs of the first to fourth elements 17 OR, and the first to fourth outputs of the second decoder 16 are connected respectively to the inputs of the first, second, fourth and third elements 17 OR, etc. For example, to execute the current microcommand it is necessary to have a microcode loop, and in the first and fourth microtacks a single signal must be present on the fourth, third, first and second outputs of the encoder 8. Such a sequence of micro orders can be obtained by looping from left to right to the combination of micro orders. in the first line of the table. 2, starting with the second column. Therefore, the line number coming from the group of outputs of the control code of the register of 2 microinstructions to the inputs of the encoder 8 is equal to one, and the column number at the outputs of the counter 6 is two. The code in counter 7, which determines the number of executed micro orders, is equal to three (by one: less than the number of issued micro orders). The value of the counting direction control bit is zero, which corresponds to the counting mode with the addition of counter 6. At the line number equal to one, a single signal is produced at the second output of the input decoder 15, as a result of which the second decoder 16 is selected. At the column number equal to two, the single the signal is produced at the third output of the second decoder 16. The signal from the third output of the second decoder 16 is fed to the input of the fourth element 17 OR, with the result that the signal 21 is generated and is present for first microtack. In the second micro-clock, by pulse 19 and at zero value of the signal 20k, the content of counter 6 is one, and one is subtracted from the contents of counter 7. The contents of register 2 microinstructions are unchanged. As a result, the column number in counter 6 becomes triple, and the code in counter 7 becomes two. According to the column number, the triple three, a single signal is generated at the fourth output of the second decoder 16. This signal enters the input of the third element 17 OR, as a result of which the signal 22 is generated. In the third micro-pulse, a pulse is added to pulse 6 to 6, as a result what its contents overflow with. The highest unit goes beyond the limits of the bit grid, and in the counter 6 there remains a code equal to zero. From the counter 7 the unit is subtracted, as a result of which its content becomes equal to one. According to the zero number of the column, a single signal is generated at the first output of the second decoder 16, as a result of which a signal 23 is generated. In the fourth micro-pulse, pulse 1 is added to the content of counter 6. By a column number equal to one, a single signal is produced at the second output of the second decoder 16, as a result of which a signal 24 is produced. One is subtracted from counter 7. The contents of counter 7 become zero, with the result that a signal 20 is generated.

In the next micro-clock pulse 1 9 and with a single value of signal 20, the next micro-command is entered into register 2 of micro-instructions, counter 6 and counter 7.

Up to this point in time, the address of the next microcommand was formed on the address part of the current microcommand in the condition monitoring unit 4. If the bit indicating the type of transition is zero (unconditional transition), then AND elements 13 are closed and the address of the next micro-command is determined directly from the address part of the current micro-command. In the conditional transition, the elements 13A are open, and the address of the next microcommand is formed depending on the value of the condition signals received from the operating circuits to the input 10 of the device. The pulse 19 is formed by the condition control unit 4, the address is entered into the address register 3, as a result of which the appropriate microcommand is selected from the microinstructions memory 1 1. Thus, the microcontrols are entered into the register 2 and the microcommand counters 6 and 7 are prepared in advance. For example, to perform this microcommand, a sequence of four micro orders is needed, in which a single signal must be present on the fourth, second, first and third outputs of the encoder 8. Such a sequence of micro orders can be obtained by looping through the right to left combinations of micro orders in the first row of the table. 2,

starting with the second column. In this case, the line number, column number, and the number of micro-orders that are issued have the same values as when executed by the scientific research institute of the preceding micro-command. The value of the control direction bit is equal to one, which corresponds to the counting mode with subtraction of the counter 6 Execute this microcommand (on

FIG. 4 for simplicity, not shown) is produced in the same way as the previous one, except that one is subtracted from counter 6 in each micro-tact. A single signal is sequentially generated at the fourth, second, first, and third outputs of the equalizer 8.

The principle of operation of the device, shown for the case with four micro-orders, is logical for any number of micro-orders. Moreover, the following relation is true:

about l- (± dist)

2 a.

where S is the number of combinations of micro orders for a functionally complete set for operation of the device (contents of Table 2);

n - the maximum number of micro-orders executed in one microcommand.

For example, when n is equal to 3, 4.5, the value of S is respectively 1,3,12. . In this device, in comparison with the prototype, it is necessary to build an encoder in half the number of decoders. Accordingly, the number of inputs to the OR elements and the corresponding links is halved. The introduction of the counting direction control bit into a microcommand is compensated for by reducing by one bit the field number in the control part of the microcommand.

Thus, the proposed device has a simpler design compared to the prototype.

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Claims (1)

FIRMWARE CONTROL DEVICE containing a memory unit (microcommands, address register, microcommand register 'clock generator, condition control unit, first and second counters and an encoder containing an input decoder, η OR elements (and = 1,2, ...) and (and-1)! / 2 h of decoders, the first group of inputs of the condition control unit connected to the group of outputs of the address code of the micro-register register, the group of information inputs of which connected to the first group of information outputs of the micro-command memory, group of address inputs of which connected to the group of information outputs of the address register, the group of information inputs of which is connected to the group of outputs of the condition control unit, the second group of inputs of which is the group of inputs of the code of the logical conditions of the device, the group of outputs of the operation code of the register of microcommands is the group of outputs of the operation code of the device, permission input the micro-register register is connected to the recording permission inputs of the first and second counters and the loan output of the second counter, the counting input of which is connected to the counting input the first Counter, the input of the register of micro registers, the input of the synchronization of the address register and the output of the clock pulse generator, the input to the 0 r. of the address register is the input of the initial installation of the device and is connected to the installation input to 0 of the second counter, the group of information inputs of which are connected to the second group of information the outputs of the memory block of microcommands, the third group of information g outputs of which are connected to. the group of information inputs of the first counter, the group of information outputs of which is connected to the inputs (and -1) </ 2 of the decoders, the group of outputs of the control code of the micro-register register is connected to the group of inputs of the input decoder, the outputs of the τth decoder (£ = 1,2 ,. .., (and-1) 1/2) are connected respectively with the ith inputs of η OR elements, the outputs of which are the control outputs of the device, the gating input of the ith decoder is connected to the ith output of the input decoder, which differs from the fact that, in order to simplify the device, the output of the control bit By adjusting the control signals of the micro-command register, it is connected - \ with the input for controlling the direction of counting; that of the first counter. 1911111 “ ^D OS