SU1095432A1 - Device for shaping variable correction effect pulses - Google Patents

Abstract

A DEVICE FORMING A PULSE VARIABLE CORRECTION EFFECT, containing a phase discriminator, the outputs of which are connected to the installation inputs of the first and second shift registers, while the information input of the phase discriminator is the first input of the device, the second input of which is the reset input of the first shift offset, the first discriminator of the first register shift, the shift input of the phase discriminator is the first input of the device, the second input of which is the reset input of the first shift offset, and the single input of the phase discriminator is the first input of the device whose second input is the reset input of the first shift offset phase discriminator, and the clock input of the first shift register, combined with the clock input of the second shift register, is the third input roystva, characterized in that, in order to simplify the apparatus by eliminating the auxiliary shift register and an AND, introduced inverter, the input of which is combined with the second input device, and the inverter output is connected to the reset input of the second shift register. 9 -

Description

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g / -. The invention relates to a technique for transmitting discrete messages and can be used, in particular, in clock synchronization devices of the receiving part of information transmission equipment. A time shift corrector is known, comprising a memory block, a NO element, a time discriminator controlled by a generator voltage, and a control unit 1. A disadvantage of the known device is high complexity. The closest to the present invention is a pulse shaping device with a variable correction effect containing a phase discriminator, the outputs of which are connected to the set inputs of the first and second shift registers, while the information input of the phase discriminator is the first input of the device, the second input of which is a reset input the first shift register, combined with the clock input of the phase discriminator, and the clock input of the first shift register, combined with the clock input of the second register the offset trap is the third input of the device, as well as the auxiliary shift register, the output of which is connected to the first input of the element I, to the second input of which the output of the second shift register is switched on and the clock input of the auxiliary shift register is the third input of device 2. A disadvantage of the known device is its complexity, due to the non-optimal way of forming a variable corrective action in the case of a phase advance clock. The purpose of the invention is to simplify the device by eliminating the auxiliary shift register and element I. The goal is achieved by the fact that the device for generating pulses of variable correction effect, containing a phase discriminator, the outputs of which are connected to the installation inputs of the first and second shift registers, while the information input of the phase discriminator is the first input of the device, the second input of which is the fault input of the first shift register, combined with the clock input of the discriminator and the clock input of the first shift register, combined with the clock input of the second shift register is a third input device introduced inverter, the input of which is combined with the second input device, and the inverter output is connected to the reset input of the second registrasdviga. FIG. Figure 1 shows a structural electrical circuit of a device for generating pulses with a variable correction effect; in fig. 2 and 3 - time diagrams of his work. The pulse shaping device of the variable correction effect comprises a phase discriminator 1, an inverter 2, a first 3 and a second 4 shift registers. The pulse shaping device of the variable correction effect operates as follows. Reading information recorded in registers 3 and 4 is carried out by high-frequency pulses (Fig. 2a and Fig. 3a), arriving at the third input of the device (from the master oscillator of the clock synchronization device, which includes the proposed device), the following frequency fi K times the transmission rate B (discrete modulation rate or wiring rate), i.e. ft KtB. The value of Kj determines the width of the zone S. For example, with the most optimal value of K 32, the value of each zone S (total q q Ki / 2, where q is the number of bits of the shift registers) is r; / 32 (where is the duration of a single message element) i.e., about 3% of the duration of the message item. If the clock synchronization pulses (these pulses are the output pulses of the clock synchronization device, which includes the proposed device), arriving at the second input of the device (Fig. 2a), are out of phase with the received message elements (Fig. 26). rcT and io-rc-r 4S (this case is shown in Fig. 2), then at the moment of lag registration, the pulse formed on the first output of phase discriminator 1 (Fig. 2d) transfers all q elements of the first shift register 3 to the unit state. From this point in time, the first output of the device (the output of the first register 3 of the shift) begins to receive correction impulses of phase addition, the frequency of which corresponds to the frequency fj of the pulses arriving at the third input of the device. The number of these pulses (Fig. 2d) is proportional to the magnitude of totcT, since at the time (Fig. 2c) the next clock pulse appeared at the second input of the device (from the clock polisher generated by the clock synchronization device) all elements of the first shift register 3 are shifted to zero. At 3S toTC.T 4-S, the number of pulses read from the first register 3 is 4. The maximum number of correction pulses that can be read from the output of the first register 3 is shifted and is achieved at the maximum possible phase lag (, (ql) -S , is equal to q (at Ki 32, q 16). If the clock synchronization pulses arriving at the second input of the device (Fig. Sv), are ahead of the phase received

message elements (Fig. 36) by the value ton to 3S (this case is shown in Fig. 3), then at the time of registering the advance pulse generated at the second output of phase discriminator 1 (Fig. Rear), all q elements of the second shift register 4 in a single state. From this point in time, at the second output of the device (the output of the second register 4 of the shift), the phase subtraction correction pulses appear, the frequency of which corresponds to the frequency f |. pulses arriving at the third input of the device (Fig. For). The number of these pulses (Fig. Ze) is proportional to the value of ton. since the translation of the second register 4 of the shift to zero (its reset) is performed by an inverted (Fig. 3g) sequence of clock pulses. / 7 d about

arriving at the second input of the device (the invert of a clock wipper is equivalent to a shift of the clock wipper by half the duration of a single message element, i.e. by the value). Thus, with 3-S-to 4-S, the number of 4 pulses read from the output of the second register is 4. The maximum number of correction pulses that can be read from the output of the second shift register 4 and appear at the maximum possible phase advance / 2 ton (q-1) s, is q (q 16).

Thus, the proposed device for generating pulses of variable correction effect is the simplest in comparison with the known ones. ilinilllMllllllllillllUnilMMIIIIIIIIIIinilllllll llinillllMMUillMIIIIIIHIilllllllllllllllllllinin fpuff, 2

Claims (1)

A DEVICE FOR FORMING PULSES OF A VARIABLE CORRECTION EFFECT, comprising a phase discriminator, the outputs of which are connected to the installation inputs of the first and second shift registers, while the information input of the phase discriminator is the first input of the device, the second input of which is the reset input of the first shift register combined with the clock input , and the clock input of the first shift register, combined with the clock input of the second shift register, is the third input of the device VA, characterized in that, in order to simplify the device by eliminating the auxiliary shift register and the And element, an inverter is introduced, the input of which is combined with the second input of the device, and the inverter output is connected to the dump input of the second shift register. / s ©> next ho>