SU1095182A1 - Device for making diagnostics of logic units - Google Patents

Abstract

A DEVICE FOR DIAGNOSTICS OF LOGICAL BLOCKS, containing a control unit, the first and second outputs of which are connected respectively to the inputs of the test register and the first switch, the output of which is connected to the input of the control unit, a comparator, the output of which is connected through a circuit. comparison with the input of the first counter, the output of which is connected to the input of the first switch, the decoder, oh tl and which is the fact that, in order to increase the equipment utilization factor, a counter, switch, two triggers are entered into it, the third and fourth inputs of the control unit through the second counter, connected to the input of the decoder, whose input through the serially connected register of tests and the second switch is connected to the output of the device and the inputs of the first switch and the comparison circuit whose output is connected to the input m per. switch, the fifth output of the control unit through the first trigger is connected to the inputs of the second switch and the first counter, the outputs of which are connected to the inputs of the second switch, second trigger and comparator, the output of the second trigger is connected to the input of the second switch, the output of the comparator is connected to the inputs of the first and second switches, the sixth output of the control unit is connected to the input of the decoder, and the control unit contains two memories, three counters, four registers, a comparison circuit, a decoder, an indicator, and The first memory through the first register is connected to the inputs of the first and second counters, the second register and the decoder, the outputs of which are connected to the inputs of the first counter, second and third registers, the third counter, the comparison circuit, the second memory, the third, fourth, fifth and the sixth output of the block, the output of the first counter through the second memory CO is connected to the input of the fourth register, the output of which is connected to the first SD output of the block and through the serially connected comparison circuit and 00 the second counter to the input of the first pa-m and blocks entry through the third PE .gistr connected to inputs of the indicator and the second register, whose output is input with cos union of comparing circuits third counter output is connected to the indicator input, the first output register is connected to the second input unit.

Description

The invention relates to computing and can be used to detect and localize computer faults. A device for diagnosing computer units is known, comprising a series-connected test drive, an input register, a test register, a code converter block, an output register and a buffer memory block, whose control input and control inputs of the output register, test register, input register and result register connected respectively to the first, second, third, fourth, and p. the outputs of the control unit, connected to the output of the test accumulator, and the result register output is connected to one of the output inputs of the output register. This device also contains a control unit and a control code register, the information input of which is connected to the output register output, the output is connected through the code converter unit with the information input of the control unit, and the control input with the sixth output of the control unit, the seventh output of which is connected to the control input of the control unit connected to the information output Ion input of the register of result Sh. The disadvantage of this device is that it provides verification and localization of faults in semiconductor RAMs contained in the checked computer unit. The closest to the present invention is a device for diagnostics of computer units, comprising, the first and second outputs of the control unit are connected respectively to the test register inputs and the first switch, the output of which is connected to the control unit input, the comparator whose output is connected through a comparison circuit the input of the first counter, the output of which is connected to the input of the first switch, the decoder 2j. A disadvantage of this device is the large amount of service information stored in the test drive. The aim of the invention is to increase the utilization rate of equipment by reducing the amount of test information. The goal is achieved by connecting a logic unit with a control unit, the first and second outputs of which are connected respectively to the inputs of the test register and the first switch, the output of which is connected to the input of the control unit, Koi napaTop, the output of which is connected via a comparison circuit with the input the first counter, the output of which is connected to the input of the first switch, the decoder, is entered a counter, switch, two triggers, the third and fourth outputs of the control unit through the second counter connecting Yeni to the input of the decoder, the output of which is connected through the serially connected test register and the second switch is connected to the output of the device and the inputs of the first switch and the comparison circuit whose output is connected to the input of the first switch, the fifth output of the control unit through the first trigger is connected to the inputs of the second JT switch and the first counter, the outputs of which are connected to the inputs of the second switch. the second trigger and comparator, the output of the second trigger is connected to the input of the second switch, the output of the comparator is connected to the inputs of the first and second switches, the sixth output of the control unit is connected to the input of the decoder, and the control unit contains two memories, three. counter, four registers comparison circuit, decoder, indicator, the output of the first memory through the first register connected to the inputs of the first and second counters of the second register and the decoder whose outputs are connected to the inputs of the first counter,; the second and third registers, the third Counter, the comparison circuit, the second memory, the third, fourth, fifth and six outputs of the block, the output of the first counter through the second memory is connected to the input of the fourth register, the output of which is connected to the first output of the block and through connected in series the comparison circuit and the second counter - with the input of the first memory, the input of the block through the third register connected to the inputs of the indicator and the second register, the output of which is connected to the input of the cpVB EN, the output of the third counter connected to the input of the indicator, you the stroke of the first register is connected to the second input of the control unit. FIG. 1 shows a block diagram of the device; in fig. 2 is a block diagram of the control unit. The device includes a control unit 1, a counter 2, a decoder 3, a register of 4 tests, a switch 5, a trigger 6, a counter 7, a trigger 8, a comparator 9, a comparison circuit 10, a switch 11. The control block 1 (Fig. 2) includes memories 12 and 13, counters 14-16 registers 17-20, decoder 21, -. indicator 22 and comparison circuit 23. The diagnosed unit is connected to the output of the device and the operation of the device begins by pressing the Start button (not shown). The diagnostic tests of the blocks are placed in the test drive - memory 12 (Fig. 2). In the event that the accumulator test is a RAM, information can be loaded into it from an external device such as a punched tape input device, a tape cassette player and other devices. Firmware providing test input to the diagnosed unit, analysis of its responses by testing the state of the unit's outputs and comparing them with the reference ones is placed in the memory control bar 13. When the Start button is pressed, the initial (zero) address of the firmware is set in the address counter 13 and is reset to the counter 16. Thereafter, the sequential reading of the micro-instructions from memory 13 into the register 17 begins and their execution. Register 17 has a field of constants and a field of micro operations. Micro-operations are decrypted in decoder 21. Under the control of one of the micro-operations, information from the constant floor registers 17 to the counter 15 of the address, setting the initial test address of the unit to be checked. Under the control of other micro-operations, information from memory 12 is counted and transmitted to data register 18. I. . Test information in memory 12 is recorded in the following order, with each test set occupying a fixed number of RAM cells, an official code that determines the type of test set, with or without checking the integrated circuits (IC) of the RAM, is written. The test set is followed by a reference information on the state of the healthy block on the test set. The service code analysis is performed by alternately sending both service codes from the constant field of register 17 to register 20, reading the service code from memory 12 and comparing them in comparison circuit 23. When the service code read from memory 12 matches with the one specified in register 20, the firmware branch is executed by modifying the address in address counter 14. The test is performed without checking the .IS RAM and then checking. Performing one elementary test of a tested block is reduced to submitting a test set to its input, polling a response and comparing it with a reference response. The supply of the test suite to the input of the diagnosed unit is performed in the following way. After resetting counter 2 (FIG. 1), trigger 6, and modifying the address in counter 15 (FIG. 2), the information from memory 12 to register 18 is read by one and then passed to test register 4 under control of counter 2 and decoder 3. After installing the first piece of information from memory 12 into register 4, the firmware adds one to counter 2 and sends the next piece of information to another group of bits of register 4 and so on until the entire register 4 is filled with a test set. The zero state of the trigger 6 ensures the transmission of the test set through the switch 5 to the input of the diagnosed block. The state of the outputs of the diagnosed unit is determined microprogrammatically through the switch 11. The state of the outputs of the diagnosed unit enters the register 19. The switch 11 provides the transfer of the output states of the diagnosed unit to the register 19 in several cycles, since its size is less than the number of contacts of the diagnosable unit block. The KOMNfyTaTopoM is controlled by the register 17 bits. After receiving the first condition information in register 19 on the status of the diagnosed block, this information is sent to register 20. The coupon information is read by the firmware from memory 12 to the register 18. The comparison of the real block response with the reference

performed in comparison circuit 23. The result of the comparison modifies the microcommand addresses and causes the firmware to branch to continue the comparison or to stop with the indication. After the end of the next elementary test, i.e., supplying the test set to the input of the diagnosed block, polling its contacts and comparing with the reference values: one is added to the counter of 16 tests. In counter 16, the current test HaiCopa number is stored. If the result does not match the reference test, the testing procedure is stopped and the state of the test counter and contacts is displayed via the indicator 22 to indicate. washable block.

Poi perform an elementary test with checking cumulative blocks. those. units 5 containing RAM RAM; unit 1 establishes trigger 6 in the unit state that through the switch 5 connects the outputs of counter 7, trigger 8 and comparator 9 to the inputs of the diagnosed unit.

Checking the RAM RAM consists of two cycles: writing test information to the NB and compiling it with random checking.

In the recording mode, the address counter 7 forms the address code of the block check, the comparator 9 - information for recording, the trigger 8 is set to one (recording mode); After writing to the block of information at all addresses, an overflow of the counter 7 occurs. The overflow signal from the output of the counter 7 arrives at the trigger 8 and transfers it to the zero state (reading mode). Counter 7 generates the addresses of information reading from the blocks, the comparator 9 - the reference information / formation, and the block 10 compares the read information with the reference one. When an inconsistency is detected, block 10 generates an error signal that blocks further operation of counter 7. At the same time, the signal is transmitted through switch 11 to control unit 1.

If no errors are detected during the check of the blocks, then the check end signal (counter overflow signal of the counter 7) is transmitted to the control unit 1 through the switch 11.

The redesign of the control unit of the device with firmware control allows to reduce the volume of service information due to the flexibility of control and significantly reduce the total amount of tests (by 3-4 times) and, consequently, the volume of test accumulators.

The introduction of a switch, triggers and a counter allows for a complete check of the NB by hardware means without increasing the volume of test programs due to the presence of the comparator hardware j and the comparison circuit.

FIG. 2

Claims (1)

DEVICE FOR DIAGNOSTIC OF LOGIC BLOCKS, containing a control unit, the first and second outputs of which are connected respectively to the inputs of the test register and the first switch, the output of which is connected to the input of the control unit, a comparator, the output of which is connected through the comparison circuit to the input of the first counter, the output of which is connected to the input of the first switch, a decoder, oh, tl, which is due to the fact that, in order to increase the utilization of equipment, a counter, a switch, two triggers are introduced into it, and the third and fourth rty inputs through second counter control unit connected to the input of the decoder which output is connected via a series register and a second test switch connected to the device output and the first input switch and comparator circuit ^ whose output is connected to the input of per-. of the first switch, the fifth output of the control unit through the first trigger is connected to the inputs of the second switch and the first counter, the outputs of which are connected to the inputs of the second switch, the second trigger and the comparator, the output of the second trigger is connected to the input of the second switch, the output of the comparator is connected to the inputs of the first and second switches , the sixth output of the control unit is connected to the input of the decoder, and the control unit contains two memories, three counters, four registers, a comparison circuit, a decoder, an indicator, and the output is first th memory through the first register is connected to the inputs of the first and second counters, the second register and the decoder, the outputs of which are connected to the inputs of the first counter, second and third registers, the third counter, the comparison circuit, the second memory, the third, fourth, fifth and sixth outputs of the block, the output of the first counter through the second memory is connected to the input of the fourth register, the output of which is connected to the first output of the block and through a series-connected comparison circuit and the second counter - with the input of the first memory, the input of the block through thirds PE '· giste connected to inputs of the indicator and the second register, whose output is connected to the input of the comparison circuit, the third counter output is connected to the indicator input, the first output. register is connected to the second input of the block.