SU1088828A1 - Apparatus for measuring the strip reserve in collecting pit - Google Patents

Abstract

1. A DEVICE FOR MEASURING A STOCK BAND IN A DRIVING WELL, containing speed sensors and an accumulator, is different in that, in order to improve the measurement accuracy and reliability of the device, it also contains a test hole punch, a test hole indicator, two pulse length sensors lanes; each containing three pulse heads X1, four OR elements, two delay elements, five memory cells, seven AND elements, a reversible counter and a pulse synchronizer, three logical blocks, and The left outputs of the pulse heads of the first pulse length sensor are connected to the inputs of the first logic unit, the outputs of which are connected to the first inputs of the first and third memory cells, the outputs of which are connected to the first inputs of the first and third elements, respectively, the second input of which is connected to the first output of the pulse synchronizer , the outputs of the first and third elements of And are connected to the first inputs of the first and second elements of the OR, respectively, and to the second inputs (dump bus g R -G - f l 1 13: v;: 7; j Ciifti, .U44a; G.U.- : A sa) the first and third memory cells, respectively, the three outputs of the pulse heads of the second pulse sensor are connected to the inputs of the second logic unit, the first and second outputs of which are connected to the first inputs of the second and fourth memory cells, the outputs of the second and fourth memory cells are connected to the first inputs of the second and the fourth elements And, the second inputs of which are connected to the second output of the pulse synchronizer, the outputs of the second and fourth elements And are connected to the second inputs of the first and second elements, respectively LI and with the second inputs (reset buses) of the second and fourth memory cells, respectively, the outputs of the first and (L of the second OR elements) are connected respectively to the first and second inputs | Dami (addition and subtraction buses) of the adder and the first and second inputs of the third the element OR, the output of the second element OR is connected to the third i (summed) input summa-; pa, the fourth input (reset bus) is connected to the output of the first X) delay element; the second outputs 30 of the pulse heads of the nepiBoro pulse length sensor are connected to the first; The primary inputs of the fifth, sixth and seventh elements are And, the second inputs of which are connected to the output of the fifth cell / EO memory, the first and second inputs of the fifth cell of memory are connected respectively to the pilot hole of the test holes and the indicator of test holes, the outputs In addition, the sixth and seventh elements And are connected to the inputs of the third logic unit, the first and second outputs of which are connected to the first and second inputs (addition and subtraction buses) of a reversible counter, respectively, and to the first and second inputs of the fourth el OR, whose output is connected to a third

Description

the (counting) input of the reversible counter, the fourth (zero) input of the reversible counter is connected to the output of the second delay element, the output of the reversible counter is connected to the fifth input of the adder, the inputs of the first and second delay elements are connected to the output of the indicator of test holes.

2. Device pop. 1, it is clear that the logical: the block contains three memory cells, three OR elements and six AND elements, and the inputs of the memory cells are the inputs of the logic block and are connected by 7G first inputs of the Two Element 4ent And each second input of the memory cell ti, is connected to the output of the corresponding element OR, the output of the first cell

the memory is connected to the second inputs of the third and sixth elements AND, the first outputs of which are connected to the inputs of the first element OR, the output of the second memory cell is connected to the second inputs of the second and fifth elements AND, the first outputs of which are connected to the inputs of the SECOND element OR, and the output the third memory cell with the second inputs of the first and fourth elements AND, the first outputs of which are connected to the inputs of the third element OR, the second outputs of the first, third and fifth elements AND are combined and are the first "output of the logic unit, and The second outputs of the second, fourth and sixth And elements are the second output of the logic unit.

The invention relates to the automation of the production of a metal strip material, namely, devices for determining the stock of a strip and a storage well.

A device is known for automatically controlling the amount of tape in an accumulation well, comprising input and output clamping rollers 1.

A disadvantage of this device is the accumulation of measurement error associated with the slippage of the rollers relative to the bands l. .

Closest to the invention to the technical essence and the achieved result is a device containing a butt welding machine, pulling rollers. installed before and after the storage well and kinematically associated with the speed sensors, and adder f23.

The disadvantages of this device are the presence of an error determining the length of the band due to the indirect method of obtaining the length of the band - integrating the speed on analog integrators, the dependence of the integration error on the speed of the band and the integration parameters, the need to reconfigure the integrators in case of a significant change in the interval between error corrections.

The purpose of the invention is to improve the measurement accuracy and reliability of the device.

The goal is achieved by the fact that a device for measuring the reserve of a strip in an accumulation well containing sensors

bandwidth and adder. additionally contains a pilot hole punch, test hole indicator, two pulsed

5 strip length sensors, each containing three pulse heads, four OR elements, two delay elements, five memory cells, seven OR elements, a reversible counter,

o pulse synchronizer, three logic blocks, with the first outputs of the pulse heads of the first pulse length sensor connected to the inputs of the first logic block, outputs

5 of which are connected to the first inputs of the first and third memory cells, the outputs of which are connected to the first inputs of the first and third elements, respectively, the second inputs of which

J are connected to the first output of the pulse synchronization, the outputs of the first and third elements I are connected to the first inputs of the first and second OR elements respectively and to the second inputs (reset buses) of the first and third memory cells, respectively, three outputs of the pulse heads of the second ± 43 pulse sensor connected to the inputs of the logical unit, the first and second outputs of which are connected to the first inputs of the second and fourth memory cells, the outputs of the second and fourth memory cells are connected to the first inputs of the second and fourth elements And, the second entrances

5 of which are connected to the second output of the pulse synchronizer, the outputs of the second and fourth elements I are connected to the second inputs of the first and second OR elements, respectively, and the second inputs (reset buses) of the second and fourth cells of the OR, respectively connected .. respectively with the first and second inputs (addition and subtraction buses) cyNiMaTopa and with the first and second inputs of the third element OR, the output of the third element OR is connected to the third (summing) input of the adder, the fourth input (buses The reset of which is connected to the output of the first delay element, the second outputs of the pulse heads of the first pulse length sensor are connected to the first inputs of the fifth, sixth and seventh elements AND, the second inputs of which are connected to the output of the fifth memory cell; the memory cells are connected respectively to the pilot hole punch and to the control indicator; the holes, the outputs of the fifth, sixth and seventh elements OR are connected to the inputs of the third logic unit, the first and second outputs of which dineny respectively, with first and second inputs (slozhe- tires. NIN and subtraction of a reversible counter with the first and second inputs of the fourth OR element, the output of which is connected to the third (counting) input. reversible counter, the fourth one (the left input of the reversible counter is connected to the output of the second delay element, the output of the reversible counter is connected to the fifth input of the adder, the inputs of the first and second delay elements are connected to the output of the indicator of control holes. The logic block contains three memories , three OR elements and six AND elements, the inputs of the memory cells being the inputs of the logic block and connected to the first inputs of the two elements AND, each second input of the memory cell is connected to the output of the corresponding the OR element, the output of the first memory cell is connected to the second inputs of the third and sixth AND elements, the first outputs of which are connected to the inputs of the first OR element, the output of the second memory cell is connected to the second inputs of the second and fifth elements AND, the first outputs of which are connected to the inputs the second element OR, and the output of the third memory cell — with the second inputs of the first and fourth elements AND, the first outputs of which are connected — with the inputs of the third element OR, the second outputs of the first, third and fifth elements AND are the first the output of the logic block, and the second outputs of the second, fourth, and sixth And elements are the second output of the logic block. . FIG. 1 shows a block diagram of the device; in fig. 2 is a block diagram of a logic unit. The device contains the first 1 and second 2 pulse sensors of the strip length, the first 3, the second 4 and the third 5 logic blocks, memory cells 6-10 from the first to the fifth, AND 11-17 from the first to the seventh elements, and OR elements 18-21 first through fourth, adder 22 reversible counter 23, first 24 and second 25 delay elements, butt welding machine 26, punch 27 control holes, indicator 28 control holes, pulse synchunizer 29. Logic unit 3 contains the first 30, second 31 and third 32 memory cells, six AND 33-38 logic elements, three OR 39 - 41 logic elements. Each of the pulse sensors 1 of the strip length contains three pulse heads with outputs 42, 43, 44 and 45, 46, 47 respectively. The outputs of each of the three pulse heads, for example, the outputs 42 - 44 of the first pulse length sensor 1, are connected to the first inputs of the cells 30 to 32 of the memory, respectively, and are also connected in pairs to the first inputs of the elements AND 33 to 38, respectively, the outputs of the cells 30, 31, 32 memories are connected in pairs with the second inputs of elements and 38 and 35, 34 and 37, 36 and 33, respectively, the first outputs of elements AND 38 and 35, 34 and 37, 36 and 38 are connected to the first and second inputs of elements OR 39, 40 and 41, respectively, whose outputs are connected to the second inputs (reset buses) of cells 30 - 32 memory the second outputs of the elements and 33, 35 and 37 are connected to the first output of logic block 3, which is connected to the first input of the first memory cell 6, and the second outputs of the elements 34, 36, 38 are connected to the second output of logic block 3, which is connected to the first input of memory cell 8. The electrical connections for the heads of the first pulse sensor 1 will be similar to the electrical connections for the heads of the second pulse sensor 2. The device operates as follows. : Pre-zeroing of the reversible counter, adder, memory cells. The signals from each of the pulse heads are fed to the inputs of the first and second logical-blocks 3 and 4, respectively, which analyze the direction of rotation of the pulse sensors 1 and 2 of length. Depending on the direction of rotation of the pulse sensors, logic blocks 3 and 4 give out pulses that arrive at the first inputs of the first and second cells 6 and 7 of the memory as the measuring rollers rotate in directions that provide an increase in the no-J margin of the storage ring (adding mode pulses), and to the first inputs of the third and fourth cells 8 and 9 of the memory while rotating the meter of the 1st rollers in opposite directions (pulse subtraction mode). The passage of the pulses of addition and subtraction is provided from elements 11-14, which transmit these pulses in case of coincidence with the pulses passing from the synchronizer of 29 pulses, a high pulse train with the period T following at times t, T where n is O, 1 , 2, ... Hi2 nT + & t, where. In order to prevent the loss of pulses in the event of their simultaneous arrival from both heads, the synchronizer pulses 29 produces two series of pulses with the test period T shifted one relative to the other by time & i, where the value ut is chosen from the condition At At T. Reset of the cells 6 -9 memory is provided by the signal from the output of the AND 11-14 elements immediately after passing the pulses to the inputs of the first and second elements OR 18 and 19. The outputs of the first and second elements OR are connected to the first and second inputs (addition and subtract buses} of the adder 22 , and with the third element OR 20, the output of which is connected to the third (summing) input of the adder 22, the number of bits of the adder corresponds to the value of L equal to the sum of the maximum value in the reserve band in the drive and the base dimensions 6 and. In where 2 from the punch of the test holes to the pulse length sensor; the distance from the indicator of the test holes to the pulse length sensor; the maximum reserve of the strip in the collection well. The correction of the accumulated in the adder 22 during prolonged operation, for example, in the case of slipping of the rollers, is signaled by the signal from the piercer 27 control holes, which pierces the hole in the weld area after welding the rolls on the butt welding machine 26. This signal controls the operation 10 memory cells, generating a single potential. The signal from the output of memory cell 10 provides for the passage of pulses from each of the pulse heads from outputs 42, 43, 44 through elements 15, 16, 17 whose outputs are connected to the inputs of logic unit 5, providing analysis of the direction of rotation of pulse sensor 1. Output signals logic block 5 is fed to the first and second inputs of the addition and subtraction bus of the reversing counter 23, as well as to the first and second inputs of the fourth element OR 21, the output of which is connected to the third (counting) input of the reversing counter 23, the number of bits of which It corresponds to the value of L band. The output signal of the indicator 28 control holes cell 10 memory is transferred to the state prohibiting the passage of pulses through the elements 15 - 17, and through the first delay element 24 produced zeroing of the adder 22. The same signal through the second delay element 25 after the reset of the adder 22 is produced overwriting in the adder 22 the contents of the reversible counter 23 and simultaneously reset it. In this way, the error accumulated during long-term operation is corrected. At the same time, the result of measuring the strip in the storage well over a long period of time corresponding to the length of the strip in three to five rolls is replaced by the measured length L of the strip, taking into account the basic dimensions P and. The measurement result recorded in the adder 22 is further used in information display and control devices in order to provide information to the operator and generate engine control signals, ensuring the maintenance of a given strip length in the drive well. The logical unit works as follows. Before starting the operation, all cells 30 to 32 of the memory are reset. With the arrival of the first pulse at time t, for example, from the second head, the memory cell 31 is transferred from O to 1. At the same time, the first pulse arrives at the inputs of the And 35 and 36 elements. However, due to the zero potential at the outputs of the cells 30 and 32 the memory impulse addition or subtraction is not generated. The second impulse can arrive at the input of the logic unit either from the third impulse head when the measuring roller rotates in the forward direction (-) or from the first impulse head when the measuring roller rotates in the opposite direction {-) in the case of a strip reversal. When the measuring roller rotates in the forward direction, the second pulse, arriving at the input of the memory cell 32 at the time instant i + Ai, where At, is the pulse following period, is remembered in the cell as a unit potential. The second pulse, passing through the same pulse through the element And 37, produces the first impulse

addin This pulse from the output of the element And 37, arriving at the input of the element OR 40, translates the cell 31 memory O

ti in the initial state

When the measuring roller rotates in the opposite direction (in the case of reversed bandwidth), the second pulse is stored in memory cell 30 and, having passed through AND 34, produces the first subtraction pulse, which also, through OR 40, translates the memory cell 31 is in the initial state O. The process of generating the Subsequent pulses of addition and subtraction is performed similarly.

The operation of the second logical unit 15 4 is similar to the operation of logical unit 3 with an obvious difference

when setting the modes of addition and subtraction.

The invention, when implemented, will allow, using discrete signal processing, to directly measure the length of the strip, which will increase the accuracy and reliability of the strip margin measurement device in metallurgical production units. This, in turn, will improve the quality of the strip material and eliminate the appearance of surface strip defects, such as a gap that occurs when the margin of the strip is less than the allowable, and the fracture that occurs when the margin of the strip exceeds the allowable, and thereby increase the production of suitable products.

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Claims (2)

1. A DEVICE FOR MEASURING A STREAM RESERVE IN A DRIVING WELL, comprising strip speed sensors and an adder, characterized in that, in order to increase the measurement accuracy and reliability of the device, it further comprises a control hole punch, a control hole indicator, two pulse length sensors strips containing three pulse heads each, four OR elements, two delay elements, five memory cells, seven AND elements, a reversible counter and a pulse synchronizer, three ^_ logical blocks, the first the strokes of the pulse heads of the first pulse length sensor are connected to the inputs of the first logical unit, the outputs of which are connected to the first inputs of the first and third memory cells, the outputs of which are connected to the first inputs of the first and third elements, respectively, AND, the second inputs! which are connected to the first output of the pulse synchronizer, the output of the first and third elements AND are connected to the first inputs of the first and second OR elements, respectively, and to the second inputs (reset buses) of the first and third memory cells, respectively, three outputs of the pulse heads of the second pulse sensor are connected to the inputs the second logical block, the first and second outputs of which are connected to the first inputs of the second and fourth memory cells, the outputs of the second and fourth memory cells are connected to the first inputs of the second and fourth of the first AND element, the second inputs of which are connected to the second output of the pulse synchronizer, the output of the second and fourth elements And are connected to the second inputs of the first and second OR elements, respectively, and with the second inputs (reset buses) of the second and fourth memory cells, respectively of the first and second OR elements are connected respectively to the first and second inputs ·; dams (addition and subtraction buses) of the adder and to the first and second inputs of the third OR element, the output of the third OR element is connected to the third ( summing up im) the adder input, the fourth input (reset bus) which is connected to the output of the first delay element, the second outputs of the pulse heads of the first pulse length sensor are connected to the first inputs of the fifth, sixth and seventh elements And, the second inputs of which are connected to the output of the fifth cell memory, the first and second inputs of the fifth memory cell are connected respectively to the punch of the control holes and to the indicator of the control holes, the output of the fifth, sixth and seventh elements And are connected to the inputs of the third logical unit, the first and second outputs of which are connected respectively to the first and second inputs (addition and subtraction buses) of the reversible counter and to the first and second inputs of the fourth OR element, the output of which is connected to the third connected to the output of the second delay element, the output of the reverse counter connected to the fifth input of the adder, the inputs of the first and second delay elements are connected to the output of the indicator of the control holes. 2. The device pop. 1, distinguished by the fact that the logical unit contains three memory cells, three OR elements, and six AND elements, and the memory cell inputs are inputs of the logical unit and are connected by the first inputs of two elements AND each, the second input of the memory cell, is connected with the output of the corresponding OR element, the output of the first memory cell is connected to the second inputs of the third and sixth AND elements, the first outputs of which are connected to the inputs of the first OR element, the output of the second memory cell is connected to the second inputs of the second and fifth AND elements, the first the outputs of which are connected to the inputs of the second OR element, and the output of the third memory cell is connected to the second inputs of the first and fourth AND elements, the first outputs of which are connected to the inputs of the third OR element, the second outputs of the first, third, and fifth AND elements are combined and are the first output of the logical block and the second outputs of the second, fourth and sixth AND elements are the second output of the logic block.