SU1083191A1 - Priority device for dynamic storage - Google Patents

Abstract

A PRIORITY DEVICE FOR DYNAMIC MEMORY, containing a request analysis block and a register, the device request inputs are inputs of a request analysis block, the register information input is a device code input, which, for the purpose of speeding up, contains element And, counter. a comparator, a pulse generator and an OR element, the output of the AND element is connected to the summing input of the counter, the output of the counter is connected to the first input of the comparator, the second input of which is connected to the register output. The comparator output is connected to the first input of the element AND, second, the swarm input connected to the output of the pulse generator, the third input of the AND element is connected to the reset input of the counter and to the last input of the device request, the last element of the IS-NOT request analysis block is connected to the first input of the OR element, the second input of the element OR is connected to the comparator output, the output of the OR element is connected to the last inputs of the AND-NOT block of the query analysis block, except for the last AND-NOT element, the outputs of the query unsciz block are the outputs of the device.

Description

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The invention relates to digital computing and can be used in control units for dynamic storage devices.

A multi-channel priority device for dynamic memory is known, containing a pulse generator, eight NAND elements, three delay elements, two OR elements, a counter, a unit addition trigger, three NOT elements, an urgent regeneration trigger, an AND element and in each channel two AND elements -NO, delay element, NOT element and response trigger. In this device, regeneration requests issued by the pulse generator are accumulated in the counter, from where they arrive for service through the lower priority channel. With a significant frequency of accessing the memory via other channels, an overflow of the counter may occur, in which case all the accumulated requests for regeneration are sent to the service through the higher priority channel C1.

The disadvantage of this device is a twofold increase in the number of regeneration cycles in comparison. with the minimum necessary, which leads to a decrease in speed,

The closest in technical essence to the proposed is a priority device containing a block of query analysis, elements. AND-NOT and register C2.

In the known device, after running the first request over a channel at the corresponding inputs of the NAND units of the other channels, a low voltage level prohibits the passage of other requests to the shared resource. If the dingly memory is used as the last, then requests for regeneration should be sent to the input of the first or second priority channel, since otherwise recovery of information at a specified time is not guaranteed. This leads to an increase in the service time of requests via other channels and a decrease in the speed of the memory as a whole.

The purpose of the invention is to increase the speed of interaction.

This goal is achieved by the fact that the priority device for dynamic space, containing the query analysis block and register, the device query inputs are the query analysis block inputs, the information input of the register is the code input of the device, the AND, counter, comparator, gene generator are entered pulses and an OR element, whereby the output of the AND element is connected to the sum-i by the peace of the input of the counter, the output of the SN.Techka is connected to the first input

the comparator, the second input of which is connected to the register output, the output of the comparator is connected to the first input of the And element, the second input of which is connected to the output of the pulse generator, the third input of the And element is connected to the reset input of the counter, and the last input of the device request, the last element IS NOT the query analysis block is connected to the first input of the OR element, the second input of the OR element is connected to the output of the comparator, the output of the OR element is connected to the last inputs of the NAND element of the query analysis block, except the last AND NONE element, Exit request analysis unit are output devices.

The drawing shows a diagram of the proposed device.

The device contains a query analysis block 1, which includes an AND-NOT 2 element, a NOT 3 element, an AND-4 element, a delay element 5, a NOT element 7, an AND-NE element 7, a delay element 8 and a NOT element 9. The device also contains an element OR 10, the element And 11, the counter 12, the comparator 13, the register 1 and the generator 15 pulses, the request inputs 16-18, the outputs 19-21, the code input 22 of the device.

Priority device works as follows.

In the initial state, the requests to the dynamic memory on the inputs 16-18

there are no logical zeros at these inputs, and the outputs of the elements AND-NOT 2.4 and 7 and the outputs of elements 5 and 8 of the delay are logical units, and at the outputs 19-21 devices there are logical zeros. Zero from input 18 sets the counter 12 to zero and at the same time prohibits the input of pulses from generator 15 through element 11 to its sum. In register 14, a code is written at input 22 that defines the maximum waiting time for regeneration requests. In the general case, this code is nonzero, therefore, at the output of the comparator 13 there is a logical one, which is fed to the output of the element OR 10.

Suppose that a request to a dynamic memory is received at the input 16 of the device. Then at all four inputs of the element AND-NOT 2 there will be logical units, and at its output a logical zero. The magnitudes of the delays of elements 5 and 8 Gu and G are comparable with the delay of signal propagation through the AND-NES elements and satisfy the relation fg Tj. . Therefore, a logical zero will appear at the inputs of the AND-HE elements 4 and 7 and will prohibit them from triggered by possible receipt and requests from inputs 17 and 18. At output 19, a unit is set, means the request is serviced from input 16, after resetting which the device will return to its initial state . Service requests from .Inputs 17 and 18. is similar. If by the time the dynamic memory with the first channel ends, both requests are present at inputs 17 and 18, then the first request goes to service from input 17, since fj fg. In the future, the request can be started again at entry 16, etc. Thus, with a significant frequency of requests received at inputs 16 and 17, the request for regeneration at input 18 is in the waiting state. Since after his arrival on. the third input of the element 11 is a logical unit, then the pulses from the generator 15 begin to flow to the summing input of the counter 12, and when its contents become equal to the code recorded in register 14, a logical zero appears at the output of the comparator 13. The latter prohibits further passage

pulses from the generator 15 to the summing input of the counter 12. At the end of the service of the next request from the inputs 16 and 17, the logical zero from the output of the NOT 6 element passes the OR 10 element and enters the inputs of the AND-NOT elements 2 and 4 before the logical zero on the outputs of elements 2 and 5. Therefore, the following request is served from input 18,

5, at the end of which the counter 12 is zeroed out and the operation of the device of the renewed e-Gs.

The application of the invention allows to increase the speed of the proposed device.

Claims (1)

A PRIORITY DEVICE FOR DYNAMIC MEMORY, containing a request analysis unit and a register, the device request inputs being the input of the request analysis unit, the register information input is the code input of the device, which means, in order to improve performance, it contains an AND element, a counter, a comparator, a pulse generator and an OR element, the output of an AND element being connected to the totalizing input of the counter, the output of the counter connected to the first input of the comparator, the second input of which is connected to the output 'register , the comparator output is connected to the first input of the And element, the second, whose input is connected to the output of the pulse generator, the third input of the And element is connected to the counter reset input and to the last input of the device request, the last AND — NOT element of the request analysis unit is connected to the first input of the OR element, the second input of the OR element is connected to the output of the comparator, the output of the OR element is connected to the last inputs of the AND elements of the query analysis block, except for the last AND gate, the outputs of the query analysis block are the outputs of the device.