SU1069153A1 - Device for measuring d/a converter linearity error - Google Patents

Description

The invention relates to a pulse and measuring technique and is intended for automatic calibration of digital-analogue converters (IDNs).

A device for measuring the error |, LP, containing a pulse generator, a counter, a trigger, a tunable DSP, a linearly rising signal generator, and a comparator, the first input of which is connected to the output of a linearly variable voltage generator, and the second with a turntable CLP output tl, is known: The disadvantage of such a device is the limited accuracy of the measurement of the linearity error due to the displacement of the initial level of the output characteristic of the pinned key.

The closest to the invention to the technical essence is a device for measuring the error of linearity of digital-to-analog converters, containing an arithmetic unit, the first input of which is. the second input is connected to the output of the sensor codes, the second input is connected to the output of the counter, and the output is connected to the indicator input, a linearly increasing signal generator, the output of which is connected to the first input of the comparator, the second input of which is connected to the input bus bar, pulse generator The input of which is connected to the first input of the first element I, the second input of which is connected to the output of the trigger and the output to the input of the counter-a, and the second element I L2.

The disadvantages of the known device are long-term measurement time, coc-TOHJuee of t + 1 cycles and insufficient measurement accuracy, since the results of the calibration of the first cycle are used to determine the linearity error of each point, which imposes increased requirements on the linearity of the linear parameters. wives in all years (+ 1 cycles.

The purpose of the invention is to improve the accuracy and speed of measurement of the error of linearity of the SDP.

This goal is achieved by the fact that, in a device for measuring the error in linearity of digital-to-analog converters, containing an arithmetic unit, the second input of which is connected to the output; the code sensor, the second input is with the counter output, and the output is with the indicator input, the ramp generator, the output of which is connected to the first comparator output p whose second input is connected to the input bus of the device, pulse generator; the output of which is connected to the -nspBof input

the first element H, the second input of which is connected to the trigger output, and the output to the input, and the second AND element, is entered the block of elements EXCLUSIVE OR or the third element K, the output of which is connected to the input of trigger, the first input through the block of elements EXCLUSIVE OR with the output of the sensor codes and the output bus device, the second input - with

0 in; the comparator, the first input of the sensor codes, the third input of the arithmetic unit and the nepBjjM input of the second element And, the second input to. which is connected to the output of the first

5 elements And, and the output - to the second input of the sensor codes.

In the drawing, ia is a block diagram of the proposed device. The device contains a sensor 1 channel, comparator 2, a rotatable D / A converter 3,

4 pulse generator, counter 5,. indicator b, generator 7 of the linearly increasing signal, the first element AND 8, the block 9 elements EXCLUSIVE 5 OR, the third element AND 10 ,. the second element And 11, trigger 12 and arithmetic unit 13, output and input 15 bus device.

The first input of sensor 1 of the codes is connected to the output of comparator 2, the second input is with the output of element I 11, and the output is with the input of block 9 elements EXCLUSIVE OR, the first input of arithmetic unit 13 and output

g bus device. The output of the generator 7 ramp signal is connected to the first input of the comparator 2, the second input of which is connected to the input bus 15,

The output of the generator 4 pulses connected to the first input element And 8, the second input of which is connected through the trigger 12 to the output of the element And 10, the first input of which is connected to the output of block 9, the second input to the output

5 of the comparator 2 and the first input element And 11, the second input of which is connected to the output of the element And 8 and the input of the counter 5, the output of which is connected to the second input of the arithmetic

0 block 13. The third input of block 13 is connected to the output of the comparator. The output of the arithmetic unit 13 is connected to the input of the indicator b.

The device works as follows.

5 way

The input 15 and output 14 buses of the device connect a turnable DAC 3,

In the initial state, at the input 0 of sensor 1, a code .o is formed, corresponding to zero of the scaleable DAC 3. The NO code is fed to the input of the DAC being turned 3 and to the inputs of block 9 NO5 or NO5, from which the signal of the logical unit is fed to The input element is AND 10. From the output of the calibrated CLP 3, the analog voltage is fed to the second input of the comparator 2, the first input of which is supplied from the generator 7 linearly increasing the itiero signal to an initial level that is smaller than the signal O from the output of the calibrated DAC 3 , Three ger 12 naho It is turned off and the signal O from its direct output prohibits the passage of the count from the generator 4 pulses through the element 8 to the input of the counter 5. The process of measuring the linearity error consists of steps during which the linearity error of the calibrated DAC 3 is determined at given m points, and p n. In the first TaKjre device operation, a generator 7 of a linearly increasing signal is started, from the output of which the voltage goes to the second input of comparator 2. When this signal reaches the initial output voltage level of the true DAC 3, the comparator .2 triggers and the logical unit signal from its output, the passage through the element And 10, includes a trigger 12, from the output — which the signal of a logical unit goes to the second input of the element And 8, allowing the passage of counting pulses from the generator of 4 pulses through the element 8 to the counter 5, the signal output from the logic unit 2 kompdratora supplied to a first input of AND gate 11, preparing it for actuation. The first counting pulse, the post from the output of the element, AND 8 to the second input of the element 11, passes through the element 11 and, arriving at the second input of the sensor 1 of the codes, ensures the change of the setting code. A new code is fed to the inputs of the scanned DAC 3, while the output of the scanned 1SHP 3 receives the analog signal to the second input of the comparator 2 and, if it exceeds the voltage level, the threshing signal from the generator 7 the first input of comparator 2, at the output of comparator 2, a logical zero signal appears. A negative voltage drop is fed to the first input of the sensor 1 code and fixes the code of the measured point. At the same time, at the output of block 9 of the EXCLUSIVE OR elements, a logical zero signal appears, which then goes to the first input of element AND 10 and prohibits Trigger 12 control from comparator 2. When the voltage to the first input of comparator 2 reaches the output voltage level of the calibrated DAC 3, the comparator 2 is triggered, and a positive voltage drop from its output goes to the third input of the arithmetic unit 13, In this case, in the memory cell of the arithmetic unit 13, at the address determined by the code sensor 1, The recorded number of pulses is proportional to the difference of the output signal set for the point being scanned and the output signal of the zero of the DAC 3 being scanned. If, when a new code is applied to the inputs of the 11АП 3, the analog signal coming from the output of the DAC 3 to the second input of the comparator 2 , does not exceed the previous level, which means that the level of the voltage supplied from the generator 7 of the linearly rising signal to the first input of the comparator 2, then the output of the comparator 2 remains the potential of the logical unit supplied to the first th input element And 11 and allowing the passage through it of the pulses of the account. At the same time, the code on the sensor 1 codes changes until the output of the comparator 2- does not receive the potential of logical zero. In this case, the operation of the device is similar to that described earlier. The last of the points to be checked is the point corresponding to the full scale code of the turned DAC 3 ots1. At the output of block 9 of the elements EXCLUSIVE OR the potential of the logical unit appears and after the comparator 2 triggers the signal of the logical unit the trigger 12, wherein the logical zero signal from the output of the trigger 12 arrives at the second input of the element AND 8 and prohibits further passage of the counting pulses to the counter, on which the recorded pulses remain. Consequently, in the memory cells of the arithmetic unit 13, the recorded number of counting pulses is proportional to the weight of the points to be turned and the number of pulses proportional to the full scale of the calibrated DAC 3. In one clock cycle of the ramp signal in the memory cells of the arithmetic unit 13, information about all calibrated points, monotonously located on the scale of the calibrated DAC 3. Thus, the verification speed of the calibrated DAC 3 increases and the measurement accuracy improves, since The error caused by a change in the angle of inclination of the linearly increasing voltage from the clock to the clock of the generator 7 of the linearly rising signal, measurement and calibration are carried out on one step of the operation of the generator 7 of the linearly increasing signal. In the arithmetic unit 13, the unit weight is calculated - the MER scale measured with the required accuracy in units of counts of pulses where, Pr, u is the number of count pulses corresponding to the code of the full scale of the scanned (, 0) ps - the decimal code of the full scale of the calibrated DAC 3, and then the measurement of the decimal code is measured at the I-th point of the scale over all measured points where n is the number of pulses recorded in the arithmetic unit 13 on the i-th clock from the 1-code sensor. The value is written into the operative memory of the arithmetic unit 13, after which the linearity error is calculated at the L-th point of the scale of the digital DAC 3. ..A, (0). (0) Ap (, zt Nt where NL is decimal. the code of the i-th point of the scale of the DAC 3 o scale is calculated. The result of the calculation is fed to the indicator 6. The device operates in the second cycle in the same way as the first one, while the O and Npuj points of the full scale of the DAC 3 being scanned are turned on. scales of the calibrated DAC 3, which, due to nonmonotonic characteristics of the monitored DAC 3, do not hit the number of points verified in the first cycle. The remaining points are checked in subsequent cycles. The measurement ends after determining the linearity error of the calibrated DAC 3 at all specified points of its scale. The accuracy of measuring the linearity error is mainly determined by the accuracy of the conditionality of the generator 7 linearity linearly increase -, dego of a signal in the range of values of the output signal of the calibrated DAC, while its slope is chosen akim, so that the number of counting pulses from generator 4 and pulses, coming luminant by one LSB the measured DAC 3 when there is enough conversion of Great for eliminating the effect of wheels (etnosti quantization time converting unit for MED determination accuracy, and w n | . The 4-pulse generator should ensure the stability of the counting pulse period over the measurement cycle. Using the device's mockup, performed for the K572PV1 microcircuits, showed an increase in the operating speed of the proposed device compared to the known average 2 to 3 times depending on the degree of monotony of the DAC being tested. At the same time, the accuracy of measurement of the linearity error of the calibrated DAC increased by approximately 10%. Thus, the technical and economic effect lies in the fact that due to the introduction of a block of elements EXCLUSIVE OR AND the third element AND the proposed device measures the error in linearity of the CPD with a high precision and speed.

Claims (1)

DEVICE FOR MEASURING THE LINEAR ERROR OF DIGITAL ANALOGUE CONVERTERS, containing an arithmetic unit, the first input of which is connected to the output of the code sensor, the second input is connected to the output of the counter, and the output is connected to the indicator input, a ramp signal generator, the output of which is connected to the first input of the comparator, the second which is connected to the input bus of the device, a pulse generator, the output of which is connected to the first input of the first element And, the second input of which is connected to the output of the trigger, and the output to the input of the counter ika, and the second element And, distingu. This is because, in order to increase accuracy and speed, an EXCLUSIVE OR element block and a third AND element are inserted into it, the output of which is connected to the trigger input, the first input through an EXCLUSIVE OR element block - with the output of the code sensor and the device output bus, the second input - with the output of the comparator, the first input of the code sensor, the third input of the arithmetic unit and the first input of the second element And, the second input of which is connected to the output of the first element And, and the output to the second input of the code sensor. SU, 1069153