SU1048517A1 - Working memory - Google Patents

Abstract

An OPERATIVE REMEMBERING NECK DEVICE containing a magnetic drive, the bit buses of which are connected to the block of shapers of discharge currents and read amplifiers, the address buses of the magnetic drive are connected to the outputs of a diode-matrix switch, the forward input of which is connected to the output of the shaper of the current recorder, the shape of the circuit breaker, and the shape of the circuit breaker, the shape of the transducer of the diode-matrix switch, the forward input of which is connected to the output of the drive, and the shape of the circuit breaker, and the shape of the transducer of the diode-matrix switch, the forward input of which is connected to the output of the drive, and the shape of the transducer, and the shape of the circuit breaker, the shape of the circuit breaker, the transducer of the current diode-matrix switch, the forward input of which is connected to the output of the drive, and the shape of the transducer and the shape of the circuit breaker. , the normirukhkhdiy element, executed in the form of a heart with a BCP with the information of an unwrapping of the discharge, separating elements, which, in particular, with the simplification of troystva, enter key, the input of which is connected to the output formats .. rovatel write current outputs rvzdepitelnk elements are connected to corresponding outputs dnodno-matrnchnogo perekpyu-. The gate, the inputs of the separating elements are combined and connected to a single pin of the normalization of the winding, the pin of which is connected to the output of the wrench, one, (L pin of the reset winding is connected to the output j of the current driver, which is strongly connected, the other j output is connected to the second diode light switch k

Description

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Isofeating refers to a computing tech, in particular, to random-access memory (RAM) of computers.

There are known RAMs on ferrite cores with BCPs with the organization of 2d2 W. with two cores per bit, in which the mode of switching cores in private cycles of the hister loop is used. zisa M-.to

Such RAMs have high speed and low power consumption, however, they are not widely used, as they have hard, demanding their implementation of the requirement not 5 only for amplitude, but also for the duration of the address write current determining the position of the operating point of the core with the BCP. on the magnetization reversal curve.

The closest to the invention is a 20 device, which contains a magnetic drive, a block, amplifiers, a readout, a block of shaper drivers of current currents, an address decoder, in the terminal stage which is used to obtain 25 dc polar current in the address bus and diode-matrix switch, read current driver,. current generator, separating elements and normalizing elements; Q number of address tires, moreover, one of the normalizing elements is made in the form of a core with a BCP with a normalizing winding and a reset winding IX. The known device, due to the stabilization of the operating point of the cores of the MAGNETIC nakatitel by normalized magnetic flux from the normalizing element, remains operable in a wide range of destabilizing factors.

However, the use of a normalizing element consisting of a core with a GTP with two winding hectares, and a separating element made in the form of a diode for each address bus leads to an increase in size and cost of the device, and also reduces the manufacturability and reliability of RAM.

The purpose of isophene is to simplify the device.

This goal is achieved by the fact that, in a RAM, a containing magnetic storage device, the discharge fields of which are connected to a block of current discharge formers and 55 reading amplifiers, the address buses of the magnetic wiper are connected to the outputs of the diode-matrix switch, the first input of which is connected with the output of the write current driver, pho {1 current reading current, the normalizing element, implemented as a core | with a BCP with normalizing winding and winding; A reset, v separating elements, a key is entered, the input of which is connected to the output of the write current driver, the outputs of the separating elements are connected to the corresponding output of the diode-matrix switch, the inputs of the separating elements are combined and connected to one output of the normalizing winding. The other input of which is connected to the key code, one winding lead is connected to the output of the read current driver, the other lead to the second input of the diode-matrix switch.

The drawing shows a functional diagram of the RAM.

The RAM contains a magnetic drive 1 in which the information cores 2 are stitched with address buses 3 and separate buses 4, a diode-matrix switch 5 with recording keys 6 and 7, combination keys 8 and 9 and diodes 10, a writing current driver 11, a current driver readout 12, a unit of formers of discharge currents and amplifiers of readout 13, the normalizing element 14, completed in the form of a core with a GPR 15 with a north 4 with a winding 16 and a reset winding 17, the separating elements 18 and a switch 19.

The device works in the following way. .

When writing information to the magnetic drive 1, a key 19 and a pair of recording keys 6 and 7 are opened in the datapad switch 5. The write address current from the write current generator 11 is distributed between the selected address bus-3 and the normalizing winding 16. In this case core 15 is normalized to its elements 14 and located on the selected address bar 2 m. information cores, where m is the number of RAM bits. The increment of the magnetic flux in the core 15 of the normalizing element iFC, and the total increment of the flux in the information cores 2 of the magnetic carrier 2 m & (related by the following relation:

(,, il.cpj, 2тАФцЦих + и; д д „4Ф where Wn is the number of turns of the normalization cable winding 16.; (- voltage on key 19 and diode 18 in normalization circuit; (coupling on key 7 and nunno 1 П in the pippno-matpig diode IP in the diode-matrix switch: - pulse duration gbk of recording f | fd - losses on the conductor respectively normalizing the & trays 16 and address bus 3. Simultaneously with the afadest current, a discharge is written to each of the discharge buses 4 The first write current, which is not the total flow increment of a pair of information cores 2, is found at the intersection of the bus with the selected address bus leads to an increase in the flow rate in one tlu / orm: on the core 2 and a decrease in the flow increment in the other core of this pair. Thus, the write discharge current determines the magnitude and polarity of the difference flow from the pair information serge dec 2, which in turn determines the useful signal when it receives information from this bit bus. Number of turns VVx, to the normal of your own winding 16 is chosen so that the full switching of the heart 15 of the normalizing element 14 s mmarnoe flow increment in information GOVERNMENTAL cores 2 on the address bus 3 will be half of the possible increments maisimalEgno flow wtih cores. At the same time, despite the fact that LF is only approximately equal to 2 m -i Fz, during recording there is a rationing of the increment of the information flow of the information |} keyboard 8 in the full switching of the normalizing core 15i and the position of the operating pin 2 of the cores 2 does not go beyond the boundaries of the linear zone in the characteristic of the record, i.e., in the dependence of the magnitude of the differential flow on the times of the “real writing current”. P (yes, the information is read into the address bus 3, the address read current is supplied, the amplitude of which is chosen sufficient for switching the information cores 2 to the initial state C-Bp). A reset winding 17 of the normalizing element 14 is included in the readout current circuit, whereby the core 15 also reads the reset state when read. While preserving the advantages of a voyesngnogo device, compounded by the regulation of the increment of the flow of information; about 1x core, the proposed RAM contains a much smaller number of normalizing and separation elements, which allows the design of the device to grow. .

Claims (1)

I REMEMBER I “NEXT DEVICE containing a magnetic storage device, the discharge buses of which are connected to the block of current-former drivers and read amplifiers, the address buses of the magnetic storage device are connected to the outputs of the diode-matrix switch, the first input of which is connected to the output of the write current driver, the read current driver, normalizing an element made in the form of a core with BCP with a normalizing winding and a discharge winding, dividing elements, which are concerned with the fact that, in order to simplify the device, a key has been entered into it, the input of which is connected to the Skoda of the current recorder of the label, the outputs of the separation elements are connected to the corresponding outputs of the diode-matrix switch--. On the other hand, the inputs of the separation elements are combined and connected to one output of the normalizing winding, the other terminal g of which is connected to the key output, one output of the reset winding is connected to the output of the read current driver, the other output is connected to the second code of the diode-matrix switch. SU <„, 1048517 1048517 2