SU1020833A1 - Device for fft processing - Google Patents

Abstract

1. A DEVICE FOR PERFORMING A QUICK FURIET TRANSFORMATION, containing three input registers, a coefficient register, a multiplier, a work register, two switches, a first adder-subtractor, four registers 1F: rx and a control unit, with the output of the First KONwyTaTopa connected to the first controller and the control unit; - a subtractor, the output of which is connected to the information input of the first register of addends info; the input input of the coefficient register is an input of the device coefficient, that is, with, To simplify the device, otio contains a second adder-subtractor, the information inputs of the first and second input registers are connected to the serial input of the first and second operands of the device, the output of the first register of the input register is connected to the third input register, the output of which is connected to the first information inputs the first and second switches, the output of the second switch is connected to the first information input of the third subtractor, the output of the second input register and the output The d register of the coefficient is connected to the inputs of the multiplier, the output of which is connected to the information input of the register of works, the year of the register of works is connected to the second informational inputs of the first and second adders and subtractors, the outputs of the first and second adders are subtracted from the first and second addendum registers respectively, the outputs of the first and second registers are connected to the information inputs,. The third and fourth registers of Elagik respectively, the outputs of the third and fourth registers of the terms, f is the outputs of the Real i and imaginary parts of the result of the device, are connected to the second information; the inputs of the first and second Kotmty tators, respectively, the first output of the control unit of the junction to yn, S is equal to the inputs of the first and second switches, the second and third outputs of the control unit are connected to the control inputs of the first and second addendum, respectively, the fourth output of the unit control is connected to the synchronization inputs of the coefficient register, the register of products, the first, second, third and fourth registers of the addends, the fifth output of the control unit is connected to the sync control panel INPUT first The first input register, the sixth output of the control unit is connected to the synchronous inputs of the second and third input registers .2. A device according to claim 1, in which the control unit comprises a clock pulse generator, a counter, two OR elements and a HE element, with the clock pulse generator connected to

Description

The INPUT of the counter, the output of the second discharge of the counter is connected to the first inputs of the first and second elements OR, the input of the element is NOT, the output of the third discharge of the counter is connected to the second inputs of the first and second elements OR, the output of the third discharge of the counter, the outputs of the first and second elements OR The outputs of the first and second bits of the counter and the output of the element are NOT respectively, but the first, second, relay, fourth, five, and sixth outputs of the control unit.

    ,, The invention relates to automation and computing and can be used to build devices that implement the Fast Fourier Transform (FFT) algorithm. A device for performing fast Fourier transform is known, which contains registers of the real and imaginary parts of factors, shapers of bitwise products, combinational accumulation of adders, a translation unit into the additional code l3, however, this device requires a large amount of equipment. Closest to the present invention is a device for performing a fast Fourier transform containing three input registers, a coefficient register, a multiplier, a work register, two switches, a first adder-subtractor, four sum registers, a control unit, and in addition a fourth input register, a second register Ficienta and the second register of works C23. A disadvantage of the known device is its complexity. (The purpose of the invention is to simplify the device. The goal is to achieve a device for performing a quick conversion, comprising three input registers, a coefficient register, a multiplier, a product register, two switches, the first adder is a subtractor, four register components and a simplification unit, and the output the first switch is connected to the first information input of the first adder-subtractor, the output of which is connected to the information input of the first sum register, the information input of the coefficient register is contains the second adder, the information inputs of the first and second input registers are connected to the serial input of the first and second operands of the device, the output of the first input register is connected to the information input of the third input register, the output of which is connected to the first information inputs of the first, and the second switch .or. output., the second switch is connected to the first information input of the second adder-subtractor, the output of the second input register and the output of the coefficient register is connected to the inputs of the multiplier, the output of which is connected to the information input of the register of products, the output of the register of products is connected to the second information inputs of the first and second adders-subtractors / outputs of the first and second receivers are connected to the first and second registers respectively, the outputs of the first and second registers of the components are connected to the information inputs of the third and fourth registers of the components, respectively, the outputs of the three rd and fourth registers terms is propelling outputs real and imaginary parts of the result of the device are connected to second inputs of the first and ynfO1A1atsionnym SECOND KP ytatopov respectively, the first control unit output is connected to the control inputs of the first and second switches, and the second. the third outputs of the control unit are connected to the control inputs of the first and second totalizer subtractors, respectively, the fourth output of the control unit is connected to the synchronization inputs of the coefficient register, the work register, the first, second, third and fourth registers of the 1 | x, the fifth output of the control unit to the synchronization input of the first, input register, the sixth output of the control unit is connected to the synchronization inputs of the second and third input registers. The control unit contains a clock pulse generator, a counter, two OR elements and a NO element, the clock pulse output is connected to the counter input, the second bit output of the counter is connected to the nepBfcjM inputs of the first and second OR elements and the input of the NO element, output of the third bit Yes, the counter connects to the second inputs of the first and second OR elements, the output of the third row of the counter, the outputs of the first and second OR elements, the outputs of the first and second bits of the counter, and the output of the element are NOT the first, second , third, fourth, fifth and sixth outputs of the control unit. FIG. 1 shows a block diagram of an apparatus for performing a fast Fourier transform in FIG. 2 - block diagram of the control unit; in fig. 3 - time diagram of the device operation. The device for performing fast Fourier transform contains three input registers 1-3, designed to receive reference samples, a register of 4 coefficients, a multiplier 5, a register of b works, switches, 7 and 8, adders-subtractors 9 and 10, registers 11-14 summands, block 15 controls, outputs 16-21 of the control unit. The control unit consists of the generator 22 clock pulses of the counter 23, the elements NOT 24, OR 25 and 26 The device for performing the fast Fourier transform performs the base operation BP.F on the base of 2 liters, ". l B.-c.w1 1. eleven . . ReA, -ReB + ReC | ReW - Jmc.Dmw Зтп Л .Jtn Б + Re С. DmwV JiTi p. ReMV, Re B j-ReG, -ReWV Oe G C Oe mW where Bj and-C are baseline counts; and, - converted; counts; W - weighting factor,,; | N - the number of samples in the source array; Re - the real part of the number; 3 is the half of the number. Consider the operation of the device when performing a basic operation. We assume that the reception in the registers is carried out at the beginning of the clock cycle for the arrival of the trailing edge of the clock pulses. FIG. 3 shows the signals arriving at the control inputs of the elements of the device for performing a fast Fourier transform from the outputs of the control unit 15. In addition, the inscriptions made indicate the operation to be performed (for totalizers and switches) and received information (for registers). In the first clock cycle, by signaling from the output 20 of the control unit 15, the real part ReB is received in the input register (operands) 2. of the initial count B. In the second clock cycle, the signal from the output 21 of the control unit 15 controls the input part (operands) 1 of the real part ReC, the initial count C, and registers the input register (operands) 3 of the register 2 according to the signal from the output 19 "of the control unit 15, the real part ReW of the weighting factor w4 is received. In the third cycle, according to the signal from the output 19 of the control unit 15, the product is, (,) ReC.j-HeW is accepted into the register of 6 products, co-selectors 7 and 8 by signals from output 16 of control subkey control unit 15 output register 3 to the inputs of adders-subtractors 9 and 10, adder-subtractor 9 in accordance with the control signals from the output 17 of the control unit 15 performs the subtraction operation, the sumrator-subtractor 10 in accordance with the input signals from the output 18 of the block 15 control - addition operation. In addition, in the register 2, the imaginary part ImBj of the initial count B is received from the output 20 of the control unit -15, and in the register 4, the imaginary signal ImW of the weight coefficient w is received in the output 4 from the output 19 of the control unit 15. In the fourth clock cycle, the signal from the output 19 of the control unit 15 controls registers 11 and 12 terms, respectively, ReA ReB, -ReiCj x xReW and ReA.ReB.j + ReCj-ReW, into the register of 6 products, the product P2 / j - ImW is accepted, into the register 3, the signal from the output 21 of the control unit 15 rewrites the contents of the register 2 (ImB-), the switches by the signal from the output 16 of the control unit 15 are connected to the inputs of the adders-subtractors 9 and 10, the output of the register 3, adders-subtractors in accordance with the signals from the outputs 17 and 18 control unit 15 performs subtraction (9) and addition (10) operations. In addition, the register 4 of the coefficients of the signal from the output 19 of the control unit 15 is assumed to be imaginary by the ImW weighing unit of the weight coefficient W, and the register 1 of the signal from the output of the 21 indicates the imaginary portion ImC.j of the initial counting C From the output 19 of the control unit 15 to the registers 13 and 14, the contents of the registers 11 and 12 are rewritten, i.e. .in register 13tReA - ReB -ReCj x JfReW; in register 14: I eA | ReB- + ReC xReW; registers 11 and 12 are taken, respectively, ImAj ,, 1TB, -ReC -ImW and ImA- 1tV -f ReC, -ImW; a register of 6 products is taken by Pjj ImW. In register 2, according to the signal from the output 20 of the control unit 15, the real part ReB of the initial count V is received. In register 4, according to the signal from the output 19 of the control unit 15, the actual part ReW of the weight factor W is received. Switches 7 and 8 are outputted from the output 16 of the block 15 the controls are connected to the inputs of adders-subtractors 9 and 10, the outputs of registers 13 and 14 of the components respectively. The totalizers-subtractors 9 and 10 in accordance with the control signals from the outputs v17 and 18, you complete the operations of addition (9) and subtraction (10 ). In the sixth cycle, registers 13 and 14 terms are rewritten to contain registers 11 and 12, respectively. Tie. IinAi + i ImBj-ReCiImWl to register 13; ImA 1tV, - + ImW KeC into register 14; In registers II and 12 terms, the real parts HeA ReB | -ReC, - l ReW -t-ImC ImW and ReA, ReC | .ReW -ImC jImW converted samples A, to register b, the product is accepted. product P4 (P ImC. -ReW. Switches 7 and o connect to the inputs of adders-subtractors 9 and 10, outputs of registers 13 and 14, respectively, adders-subtractors in accordance with the signals coming from outputs 17 and 18 of the control unit 15, perform operations subtracting (9) and adding (10). In register 3, the real part ReHj of the initial count i + j I is taken into register 1 - the real part ReCj + t of the initial counting In register 4, the real part of the weight factor W is recalled in the seventh clock cycle registers 13 and 14 of the terms are rewritten and issued to The output of the device is the contents of registers 11 and 12 of the terms, i.e. register 13; Non-A- into register 14; registers 11 and 12 receive, respectively, the imaginary parts ImAj + and 1tAc of the converted samples Ai4-i and A ;, the register B of works is accepted the product .ReC, .- ReW Switches 7 and 8 connect the output of register 3 to the inputs of adders-subtractors 9 and 10 that perform the operations of subtraction and comparison, respectively. In register 4, the imaginary part ImW of the weighting factor W is received, in input register 2, the imaginary part 1tV | reference reading b-. In the eighth cycle, the registers 13 and 14 of the terms are rewritten and the contents of the registers 11 and 12 of the terms, i.e. 1 tА, in register 13; ImA - in register 14; registers 11 and 12 are taken respectively HeB, -C.1-ReG 4 ReA +2 ReBJ4. + + ReC, the register B of works takes the product Rj, .. ReC; -fmW. In register 3, the imaginary part 1 of the initial count B is received, the switches 7 and 8 connect the output of the register 3 to the inputs of adders-subtractors 9 and 10, which perform the subtract and add operations, respectively; the imaginary portion ImCj of the initial count C f is entered in register 1 4, the imaginary part ImW of the WM weight coefficient is taken. Next, the operation of the device is similar. The advantage of the proposed device over the known one consists in a smaller number of registers and smaller number of information inputs of the switches.

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Claims (2)

1. DEVICE FOR PERFORMING FAST FOURIER TRANSFORM, containing • three input registers, coefficient register, multiplier, product register, two switches, the first adder-subtractor, four terms of terms and the control unit, and the output of the First switch is connected to the first information input of the first adder - a subtractor, the output of which is connected to the information input of the first register of terms, the information input of the coefficient register is the input of the coefficient of the device, which means that, with In order to simplify the device, it contains a second adder-subtracter, the information inputs of the first and second input registers connected to the serial input of the first and second operands of the device, the output of the first input register connected to the information input of the third input register, the output of which is connected to the first information inputs of the first and the second switches, the output of the second switch is connected to the first information input of the second adder-subtractor, the output of the second input register and the output of the register and the coefficient is connected to the inputs of the multiplier, the output of which is connected to the information input of the product register, the output of the product register is connected to the second information inputs of the first and second adders-subtracters, the outputs of the first and second adders-subtracters are connected to the information inputs of the first and second registers of the slug and the second slagaekilh registers connected to the data inputs of the third and fourth registers respectively terms, the output _e tret- its registers and fourth terms are I signal output g th imaginary parts of the result ustroyst-j. VA, connected to the second information inputs of the first and second switches, respectively, the first output of the control unit is connected to the 2 control inputs of the first and second switches, the second and third outputs of the control unit are connected to the control inputs of the first and the second adders-subtracters, respectively, the fourth output of the control unit is connected to the synchronizing inputs of the coefficient register, the product register, the first, second, third and fourth registers of terms, the fifth output of the control unit The key to the clock input of the first input register, a sixth output of the control unit is connected to the clock input of the second and the third input registers. > 2. The device according to claim 1, except that the control unit comprises a clock pulse generator, a counter, two OR elements and a NOT element, and the output of the clock generator is connected to [counter input, the output of the second discharge of the counter is connected to the first the inputs of the first and second elements OR and the input of the element NOT, the output of the third category of the counter is connected to the second inputs of the first and second elements of the OR, the output of the third category of the counter, the outputs of the first and second elements of the OR, the outputs of the first and second bits of the counter and the output of the element NOT that are respectively first, second, third, fourth, and sixth pyatm output control unit. '*. ''