SU1003320A1

SU1003320A1 - Device for discriminating the last pulse in a train

Info

Publication number: SU1003320A1
Application number: SU803001788A
Authority: SU
Inventors: Владимир Николаевич Бессмертный; Геннадий Мухитдинович Тураходжаев
Original assignee: Предприятие П/Я В-8025
Priority date: 1980-11-06
Filing date: 1980-11-06
Publication date: 1983-03-07

Description

Изобретение относится к импульсной технике и может быть использовано в устройствах обработки информации .The invention relates to a pulse technique and can be used in information processing devices.

Известно устройство выделения первого и последнего импульсов в пачке, содержащее два триггера, два элемента И, счетчик импульсов, вход которого соединен с первым входом устрой- Ю ства, а выходы связаны с первыми входами схемы совпадения, и счетный.A device is known for extracting the first and last pulses in a packet, containing two triggers, two AND elements, a pulse counter, the input of which is connected to the first input of the device, and the outputs are connected to the first inputs of the coincidence circuit, and counting.

триггер, вход которого соединен со вторым входом устройства, а один вы ход подсоединен ко второму входу схе№ совпадения, выход которой соединен со входом формирователя, ко второму входу которого присоединен перч вый вход устройства, входы управления прямым и обратным счетом счетчика импульсов подключены к выходам счетного триггера, первый вход первого элемента И присоединен к первому входу устройства,.второй вход первого элемента И подключен к выхо- , ду счетного триггера, управляющего обратным счетом счетчика импульсов, выход первого элемента И соединен с первым входом первого триггера,с первым входом второго элемента И и с третьим входом формирователя, выход схемы совпадения соединен со вторыми входами первого и второго триггеров, выход первого из которых соединен со вторым входом второго элемента И, выход которого подключен к первому входу второго триггера, выход ко которого подключен к третьему входу первого элемента И flj.a trigger whose input is connected to the second input of the device, and one output is connected to the second input of the coincidence circuit, the output of which is connected to the input of the driver, the second input of which is connected to the first input of the device, the inputs for controlling the forward and backward count of the pulse counter are connected to the outputs counting trigger, the first input of the first element And is connected to the first input of the device. the second input of the first element And is connected to the output of the counting trigger controlling the countdown of the pulse counter, the output of the first element And is connected to the first input of the first trigger, with the first input of the second element And and with the third input of the driver, the output of the matching circuit is connected to the second inputs of the first and second triggers, the output of the first of which is connected to the second input of the second element And, the output of which is connected to the first the input of the second trigger, the output of which is connected to the third input of the first element And flj.

Недостатком устройства является то, что сначала осуществляется определение количества импульсов в пачке, затем выделение последнего импульса в следующей пачке, т.е. возможно выделение последнего импульса только в каждой второй пачке и при условии постоянного числа импульсов в пачках.The disadvantage of this device is that first the number of pulses in the packet is determined, then the last pulse in the next packet is selected, i.e. it is possible to isolate the last pulse only in every second packet and subject to a constant number of pulses in the packets.

Наиболее близким по технической сущности к предлагаемому является устройство, содержащее первый триггер , первый вход которого соединен с шиной входных импульсов, а выход соединен с первым входом первого элемента совпадения, второй триггер, первый выход которого соединен с первым входом второго элемента совпадения, второй вход которого соединен со вторым входом первого элемента совпадения и шиной тактовых импульсов, счетчик импульсов, разрядные выходы которого соединены с разрядными входами делителя частоты, выход которого соединен с первым входом третьего элемента совпадения, последовательно со счетчиком импульсов соединены распределитель импульсов и коммутатор, сигнальный вход которого соединен со $ вторым входом первого элемента совпадения и входом распределителя импульсов £ 2J .The closest in technical essence to the proposed device is a device containing a first trigger, the first input of which is connected to the input pulse bus, and the output is connected to the first input of the first coincidence element, the second trigger, the first output of which is connected to the first input of the second coincidence element, the second input of which connected to the second input of the first coincidence element and the clock bus, a pulse counter, the bit outputs of which are connected to the bit inputs of the frequency divider, the output of which is connected to the first input of the third coincidence element, a pulse distributor and a switch are connected in series with the pulse counter, the signal input of which is connected to the $ second input of the first coincidence element and the input of the pulse distributor £ 2J.

Недостатком устройства является низкая помехоустойчивость, так как Ю одиночный импульс на входе устройства способен запустить счетчик импульсов, что отрицательно сказывается на определении периода следования истинной серии импульсов, кро- 15 ме того, данное устройство громоздко из-за применения сложных элементов, таких как распределитель импульсов и коммутатор.The disadvantage of this device is its low noise immunity, since a single pulse at the input of the device can start the pulse counter, which negatively affects the determination of the period of the true series of pulses, in addition, this device is cumbersome due to the use of complex elements such as a pulse distributor and switch.

Цель изобретения - повышение поме-20 хоустойчивости и упрощение устройства .The purpose of the invention is to increase the room-20 resilience and simplify the device.

Поставленная цель достигается тем, что в устройство для выделения последнего импульса в пачке, содержа- 25 щее первый триггер, первый вход которого соединен с шиной входных импульсов, а выход соединен с первым входом первого элемента совпадения, второй триггер, первый выход которого соединен с первым входом второго элемента совпадения, второй вход которого соединен со вторым входом первого элемента совпадения и шиной тактовых импульсов, счетчик импульсов , разрядные выходы которого соеди- 35 йены с разрядными входами делителя частоты, выход которого соединен с первым входом третьего элемента совпадения, введен элемент ИЛИ, выход которого соединен с вторым входом 40 первого триггера и первым входом второго триггера, второй выход которого подключен к третьему и четвертому входам первого триггера, выход которого соединен с вторым входом второ- 45 го триггера, а первый выход первого триггера подключен' к второму входу третьего элемента совпадения, выход которого соединен с выходной шиной устройства и первыми входами элемен- §q та ИЛИ и счетчика импульсов, первый выход которого подключен ко второму входу элемента ИЛИ, при этом выходы первого и второго элементов совпадения соединены соответственно с вторым входом счетчика импульсов и первым входом делителя частоты.This goal is achieved by the fact that in the device for separating the last pulse in a packet containing 25 the first trigger, the first input of which is connected to the input pulse bus, and the output is connected to the first input of the first coincidence element, the second trigger, the first output of which is connected to the first the input of the second coincidence element, the second input of which is connected to the second input of the first coincidence element and the clock bus, a pulse counter, the bit outputs of which are connected to the 35 inputs of the frequency divider, the output which is connected to the first input of the third match element, an OR element is introduced, the output of which is connected to the second input 40 of the first trigger and the first input of the second trigger, the second output of which is connected to the third and fourth inputs of the first trigger, the output of which is connected to the second input of the second 45 trigger, and the first output of the first trigger is connected to the second input of the third matching element, the output of which is connected to the output bus of the device and the first inputs of the OR §q element and pulse counter, the first output of which The key to the second input of the OR gate, the outputs of the first and second matching elements respectively connected to the second input of the pulse counter and the first input of the frequency divider.

На чертеже представлена структурная схема устройства.The drawing shows a structural diagram of a device.

Устройство содержит триггеры 1 и 60 2, элементы 3-5 совпадения, счетчик б импульсов, делитель 7 частоты,элемент 8 ИЛИ, шину 9 входного сигнала, шину 10 тактовых импульсов и выходную 11 шину устройства.The device contains triggers 1 and 60 2, elements 3-5 matches, pulse counter b, frequency divider 7, element 8 OR, input signal bus 9, bus 10 clock pulses and output bus 11 of the device.

Устройство работает следующим образом.The device operates as follows.

Первый приходящий на шину 9 импульс пачки по переднему фронту устанавливают триггер 1 в состояние, когда на его выходе появится сигнал, разрешающий через элемент 3 прохождению тактовых импульсов с шины 10 на вход счетчика 6, который подсчитывает количество тактовых импуль10 сов до прихода второго импульса пачки .The first burst pulse arriving at bus 9 on the leading edge sets trigger 1 to the state when a signal appears at its output, allowing through the element 3 the passage of clock pulses from bus 10 to the input of counter 6, which counts the number of clock pulses 10 s before the second burst pulse arrives.

Таким образом определяется период следования импульсов, а код, зафиксированный в счетчике 6, соответству15 ет периоду повторения импульсов во входной последовательности и используется для установки коэффициента деления делителя 7.In this way, the pulse repetition period is determined, and the code recorded in counter 6 corresponds to the pulse repetition period in the input sequence and is used to set the division coefficient of the divider 7.

Второй импульс входной последова2Q тельности устанавливает триггер 1 в . исходное состояние, атриггер 2 - в состояние, противоположное исходному, и на первый вход элемента 4 поступает разрешающий потенциал, позво25 ляющий прохождение тактовой частоты на второй вход делителя 7.The second pulse of the input 2Q sequence sets a 1-volt trigger. initial state, atrigger 2 - to the state opposite to the initial one, and the resolving potential arrives at the first input of element 4, allowing the passage of the clock frequency to the second input of the divider 7.

В результате устройство производит самонастройку на частоту входных импульсов, а с выхода делителя 7.снимается последовательность импульсов, ·. период следования которых равен периоду следования входной последовательности. Если второй импульс не поступает на шину 9 устройства, то переполнение счетчика 6 вызывает по35 явление импульса на его втором выходе, который через элемент 8 восстанавливает триггеры 1 и 2 в исходное . состояние.As a result, the device performs self-tuning to the frequency of the input pulses, and the pulse sequence is removed from the output of the divider 7., ·. the repetition period of which is equal to the repetition period of the input sequence. If the second pulse does not enter the device bus 9, then the overflow of the counter 6 causes a pulse to appear at its second output, which through element 8 restores triggers 1 and 2 to the original one. state.

Третий импульс входной последова40 тельности, если он принадлежит пачке, поступает на второй инверсный вход элемента 5 одновременно с импульсом на выходе делителя 7 и препятствует появлению импульса на выходной шине 45 11 устройства.The third pulse of the input sequence, if it belongs to the packet, enters the second inverse input of element 5 simultaneously with the pulse at the output of the divider 7 and prevents the pulse from appearing on the output bus 45 11 of the device.

В случае прекращения импульсной последовательности на шине 9 устройства импульс с выхода делителя 7 поступает через элемент 5 на выходную 5Q шину 11 устройства. Этот импульс является последним в пачке и указывает на конец пачки импульсов. Одновременно этот импульс сбрасывает счетчик б и триггеры 1 и 2 в исходное rj состояние. Следующий импульс, проходящий вне пачки, считывается импульсом, принадлежащим новой серии.In the case of the termination of the pulse sequence on the bus 9 of the device, the pulse from the output of the divider 7 passes through element 5 to the output 5Q bus 11 of the device. This pulse is the last in the packet and indicates the end of the pulse train. At the same time, this pulse resets counter b and triggers 1 and 2 to the initial rj state. The next pulse passing outside the packet is read by a pulse belonging to the new series.

Предлагаемое устройство для выделения последнего импульса в пачке отличается от прототипа повышенной помехоустойчивостью от одиночного импульса на входе устройства, так как исключается возможность запуска счетчика импульсов этим сигналом, в ре65 зультате чего устраняется погреш1003320 ность в определении периода следования истинной серии импульсов. Устройство обладает более простой конструкцией, так как не содержит громоздких элементов, например распределителя импульсов и коммутатора.The proposed device for isolating the last pulse in a packet differs from the prototype in increased noise immunity from a single pulse at the input of the device, since it excludes the possibility of starting the pulse counter with this signal, which eliminates the error 1003320 in determining the period of repetition of a true series of pulses. The device has a simpler design, since it does not contain bulky elements, such as a pulse distributor and switch.

Claims

The invention relates to a pulse technique and can be used in information processing devices. A device is known for separating the first and last pulses in a packet containing two flip-flops, two AND elements, a pulse counter, the input of which is connected to the first input of the device, and the outputs are connected to the first inputs of the coincidence circuit, and the counting one, the trigger whose input is connected with the second input of the device, and one output is connected to the second input of the coincidence circuit, the output of which is connected to the input of the imaging device, to the second input of which the first input of the device is connected, the control inputs of the forward and reverse counts of the pulse counter connected to the outputs of the counting trigger; the first input of the first element I is connected to the first input of the device; the second input of the first element I is connected to the output of the counting trigger controlling the counting of the pulse counter; the output of the first element I is connected to the first input of the first trigger with the first input the second element And with the third input of the imager, the output of the coincidence circuit is connected to the second inputs of the first and second triggers, the output of the first of which is connected to the second input of the second element And, the output of which Yuchen to the first input of the second trigger, the output of which is connected to the third input of the first element AND fliJ. The drawback of the device is that the number of pulses in a burst is first determined, then the last pulse in the next burst is selected, i.e. it is possible to select the last pulse only in every second burst and under the condition of a constant number of pulses in the burst. The closest in technical essence to the present invention is a device comprising a first trigger, the first input of which is connected to the input pulse bus, and the output is connected to the first input of the first matching element, the second trigger, the first output of which is connected to the first input of the second matching element, the second input which is connected to the second input of the first coincidence element and the clock pulse bus, the pulse counter, the bit outputs of which are connected to the bit inputs of the frequency divider, the output of which is from The pulse preamplifier and the switch are connected in series with the pulse counter and the switch input, the signal input of which is connected to the second input of the first coincidence element and the pulse distributor 2 j. The disadvantage of the device is low noise immunity, since a single pulse at the input of the device is able to start a pulse counter, which negatively affects the determination of the period following the true pulse train, and this device is cumbersome due to the use of complex elements such as a pulse distributor and switch . The purpose of the invention is to increase pom resistance and simplify the device. The goal is achieved by the fact that the device for selecting the last pulse in a packet containing the first trigger, the first input of which is connected to the bus of input impulses, and the top 2 {second connected to the first input of the first element of coincidence, second trigger, the first output of which is connected to the first input of the second coincidence element, the second input of which is connected to the second input of the first coincidence element and the clock pulse bus, a pulse counter, the bit outputs of which are connected to the bit inputs of the frequency divider, the output of which It is connected to the first input of the third element of the coincidence; an SHI element is introduced, the output of which is connected to the second input of the first trigger and the first input of the second trigger, the second output of which is connected to the third and fourth inputs of the first trigger, the output of which is connected to the second input of the second trigger, and the first output of the first trigger is connected to the second input of the third match element, the output of which is connected to the output bus of the device and the first inputs of the OR element and the pulse counter, the first output of which is connected to oromu input OR gate, the outputs of the first and second elements matcher connected respectively to a second input of the pulse counter and the first input of the frequency divider. The drawing shows a block diagram of the device. The device contains the triggers 1 and 2, the elements 3-5 matches, a pulse counter 6, a frequency divider 7, an OR element 8, an input signal bus 9 a clock pulse bus 10, and an device output bus 11. The device works as follows. The first pulse of the stack arriving at bus 9 on the leading edge sets the trigger 1 to the state when its output is driven by a signal allowing through the element 3 the passage of clock pulses from bus 10 to the input of counter 6, which counts the number of clock pulses before the second pulse arrives packs. Thus, the pulse following period is determined, and the code recorded in counter 6 corresponds to the pulse repetition period in the input sequence and is used to set the division factor of divider 7. The second pulse of the input sequence sets trigger 1 to its original state, and trigger 2 the opposite of the original, and at the first input of element 4, the resolving potential arrives, allowing the passage of the clock frequency to the second input of the divider 7. As a result, the device produces tuning to the frequency of the input pulses, and from the output of the divider 7, a sequence of pulses is removed, the follow-up period of which is equal to the follow-up period of the input sequence. If the second impulse does not arrive at the device bus 9, then the overflow of the meter B causes a pulse at its second output, which through element 8 restores the triggers 1 and 2 to the initial state. The third impulse of the input sequence, if it belongs to the bundle, arrives at the second inverse input of element 5 simultaneously with the impulse at the output of divider 7 and prevents the appearance of a pulse at the output bus 11 of the device. In the event of the termination of the pulse sequence on the device bus 9, a pulse from the output of the divider 7 goes through element 5 to the output bus 11 of the device. This pulse is the last one in the burst and indicates the end of the burst. At the same time, this pulse resets counter b and triggers 1 and 2 to the initial state. The next impulse passing outside the pack is read by the impulse belonging to the new series. The prepulsed device for selecting the last pulse in a packet differs from the prototype by increased noise immunity from a single pulse at the device input, since the possibility of triggering the pulse counter by this signal is eliminated, thereby eliminating noipeui in determining the follow-up period of the true pulse train. The device has a simpler design, since it does not contain bulky elements, such as the impulse distributor and the switch. The invention The device for selecting the last pulse in a packet containing the first trigger, the first input is connected to the input pulse bus, and the output is connected to the first input of the first matching element, the second three ger, the first output of which is connected to the first input of the second matching element, the second the input of the latter is connected to the second input of the first coincidence element and the clock pulse bus; the pulse counter, the bit outputs of which are connected to the bit inputs of the frequency divider, the output of the latter is connected to ne By the third input of the third coincidence element, this is because, in order to increase the noise immunity and simplify the device, an OR element is entered into it, the output of which is connected to the second input of the first trigger and the first input of the second trigger, the second output of which is connected to the third and the fourth inputs of the first trigger, the output of which is connected to the second input of the second trigger, and the first input of the first trigger is connected to the second input of the third match element, the output of which is connected to the output bus of the device and the first the inputs of the OR element and the pulse counter, the first output of which is connected to the second input of the OR element, while the outputs of the first and second elements of the match are connected respectively to the second input of the pulse counter and the first input of the frequency divider. Sources of information taken into account during the examination 1. USSR author's certificate No. 531268, cl. H 03 K 5/13, 1976,

2. USSR author's certificate number 725214, cl. H 03 K 5/13, 1980. (prototype).