SU1001470A1 - Switching device - Google Patents

Description

(54) SWITCH

Ieobretenle relates to switching technology.

Switches are known to include counters, a descrambler, generators, a trigger, a comparator, and a delay element 1.

 The disadvantages of the known devices are low speed.

The closest technical solution to the proposed is a switch containing a channel counter, the counting input of which is connected to the clock generator output, information inputs are connected to the input buses, and the outputs are connected via a decoder to a group of output buses and directly to the first inputs of the comparison unit, the second inputs of which connected to the outputs of the pulse counter, as well as the delay element And the trigger, a single output of which is connected to the start input of the high-frequency generator 2.

The disadvantages of the known device are low speed,

The purpose of the invention is to increase the speed of the switch.

This goal is achieved by the fact that in the switch containing the channel counter, the counting input of which is connected to the clock generator output, the information inputs are connected to the input buses, and the outputs are connected via a decoder to the output bus group and directly to the first inputs of the comparison unit, the second inputs of which connected to the outputs of the pulse counter, as well as a delay element and a trigger, a single output

10 of which is connected to the start input of a high-frequency generator, two formers, two OR elements, four H elements and an inverter, whose input is connected, are introduced; the output of the null 15 channel of the decoder and the first input of the first element I, and the output connected to the first input of the second element I, the second input of which is connected to the output of the clock generator,

20 by the second input of the first element AND and the first input of the first element OR, the third input is with the third input of the first element AND, the first output of the comparison unit and the zero input of the trigger, and the output is connected to the first input of the second OR element, the second input of which is connected through the first driver with the output of the first element And, the first output bus and

30 reset input pulse counter.

and the output is connected to a single trigger input, the zero output of which is connected to the second input of the first OR element, whose output through the second driver is connected to the input of the delay element, the output of which is connected to the second output bus, while the second and third outputs of the comparison unit are connected to the first inputs the third and fourth elements And, respectively, the second inputs of which are combined and connected to the output of the high-frequency generator; the output of the third element And is connected to the third output bus and the subtractive input of the counter ik pulses, and the output of the fourth element And - to the fourth output bus and the summing input of the pulse counter.

The drawing shows the functional diagram of the switch.

The switchboard contains a counter of 1 channels, the counting input of which is connected to the output of the clock generator 2, the information inputs are connected to the input buses 3, and the outputs are connected via a decoder 4 with a group of output buses 5 and directly to the first inputs of the comparison block b, the second inputs of which are connected to the outputs pulse counter 7, delay element 8, trigger 9, a single output of which is connected to the start input of the high-frequency generator 10, an inverter 11 whose input is connected to the output of the zero channel of the decoder 4 and the first electrical input H 12, and the output is connected to the first input element And 13, the second input of which is connected to the output of the clock generator 2, the second input of the element And 12 and the first input of the element OR 14, the third input with the third input of the element And 12, the first output of the block b comparison and zero input trigger 9, and the output is connected to the first input element OR 15, the second input of which through the driver 16 is connected to the output element And 12, the output bus 17 and the reset input of the counter 7 pulses, and the output is connected to a single input trigger 9, zero output which connect n with the second input of the element OR 14, whose output through the driver 18 is connected to the input of the delay element B, the output of which is connected to the output bus 19, the second and third outputs of the comparison block b are connected to the first inputs of the elements 20 and 21, respectively, the second inputs of which combined and connected to the output of the high-frequency generator 10, the output of the element And 20 is connected to the output bus 22 and the subtracting input of the counter 7 pulses, and the output of the element And 21 to the OUTPUT bus 23 and the summing input of the counter 7 pulses.

The switch works as follows.

With centralized and remote switching, address and cyclic operation modes are provided. Before the start of work, the initial installation of the channel 1 counter to the position corresponding to the first channel number in the cycle or the selected channel number in the address mode is performed. The decoder 4 converts the counter code 1 of the channel b control signals to enable a specific channel during centralized switching. Channel switching is performed by pulses of the clock generator 2, arriving at the counting input of the counter of 1 channels. In remote switching, the output code of the channel counter 1 is converted into a pulse number and from the output of the high-frequency generator 10 a certain number of pulses goes to the remote switch, where it sets its channel counter to the position corresponding to the selected channel number, the switch generates a Reset signal, producing a counter reset 7 pulses and simultaneously arriving at a remote switch to reset its channel counter, which ensures synchronous operation of these devices. When the remote switch is operating, a Reset signal occurs when the power is turned on to provide synchronization at the start of the operation, and then during operation at the selection of each zero channel. The total number of switching channels, as a rule, is divided into groups of 10 channels each. In this case, the reset occurs on one zero channel in each decade. When operating in cyclical mode, the subsequent number of the switched on channel differs from the previous one always by one, and in the absence of a reset of the pulse counter 7 at the beginning of the conversion, the number of pulses produced by the high-frequency generator 10 is always 1.

Thus, in a cyclic mode of operation, the code conversion time is constant, independent of the number of the switched on channel and the minimum time for issuing one pulse of the high-frequency generator 10. The counter 7 of pulses is reversible, allowing both addition and subtraction. When splitting channels into groups of 10, it is advisable to use a binary number counter. The comparison block BL compares the codes of the counter 1 of the channels and of the counter 7 pulses with the output of the Equality signal, if these codes are equal, which determines the moment of the conversion number. In addition, the block b comparison

performs bitwise comparison of the higher two bits of the codes, which allows to determine the difference between them. When the counter 7 pulses operate in a binary-decimal code, this makes it possible to determine whether the difference exceeds four or not. If the difference between the codes is more than four, and the new source code of the counter 1 channel is larger than the previous one, or the difference is less than four, and the new source code is smaller than the previous one, the comparison block b generates an output signal that determines the operation of the counter 7 pulses in the subtraction mode if the difference of the codes is less than four and the new source code is larger than the previous one or the difference is greater than four, and the new source code is smaller than the previous one, the comparison block b generates an output signal that determines the operation of the pulse counter 7 in the addition mode. Depending on the output signals of the comparison block b, the pulses of the high-frequency generator 10 pass either through the element AND 20 or through the element 21 to the subtracting or summing 11 a1 input of the counter 7 of pulses and through the corresponding bus 22 or 23 go to the external switch. In the address mode, for any combination of the previous and subsequent source codes, the number of pulses of the transformed code does not exceed five. When the next pulse of the clock oscillator 2 arrives, the state of the channel counter 1 changes and a signal is generated on one of the elements 12 or 13 depending on whether a reset is required at the start of the conversion. If the conversion goes with an initial reset, then a reset pulse is emitted to the remote switch from the output of the element and 12. In this case, the high-frequency generator 10 is turned on after the passage of the reset pulse to the remote switch, i.e. along its back edge. The output signal of the element 12 is fed to the shaper 16, the output pulse of which passes through the element OR 15 to the single input of the trigger 9. The trigger 9 is set to the single state and its single output signal turns on the high-frequency generator 10, the pulse counter 7 begins to work and the necessary the number of pulses in the remote switch, which set its counter to the position corresponding to the number of the switched on channel. The operation of the high-frequency generator 10 continues until the comparison unit 6 generates a signal corresponding to the sign equality. This output signal resets trigger 9 and high-frequency generator 10 turns off before the next clock pulse of generator 2 arrives. In the absence of a reset pulse at the beginning of the conversion, clock pulses of generator 2 pass through elements 13 and OR 15, and set trigger 9 to one, on high-frequency generator 10 and the issuance of pulses in a remote switch occurs on the leading edge 0 clock pulses of the generator 2.

The trigger 9 is reset and the high-frequency generator 10 is also turned off according to the output signal of the comparison block b, which corresponds to the 5th sign of equality.

Thus, the trigger 9 is set to a single state on the leading or trailing edge of clock pulses depending on the presence of a reset pulse at the beginning of the transformation, which corresponds to the moment of the beginning of the conversion, and is reset by the sign signal of equality, which corresponds to the moment of the end of the formation. The time during which the trigger 9 is in the one state corresponds to the code conversion interval. Zero output signal of the trigger 9 is fed to the input element OR 14. At the first input

0 element OR 14 receives the clock pulses of the generator 2; If the codes are equal and the time for the conversion of the code is not required, for example, for multiple measurements at the same address, 5 trigger 9 is in the cleared

state, its zero output signal passes the clock pulses of the generator 2 through the element OR 14 to the shaper 18, which forms the pulse at the rear edge of the clock pulses. End of operation. If the codes are unequal, then the trigger 9 is set to one state — and the clock pulses through the element OR 5 14 do not pass, the formation of pulses. The end of the operation occurs on the front that occurs at the time of the end of the conversion when it drops. with trigger 9 and there is a front on the Q output of the element OR 14.

Signal The end of a remote switching operation occurs with a delay equal to the time of code conversion and changing with it. This improves performance compared to

5 with the choice of a constant delay corresponding to the maximum code conversion time. From the output of the imaging unit 18 pulses arrive at element 8.

Claims (2)

0 Thus, the present invention, in comparison with the known, allows to increase the switch speed during remote switching by signal generation. The end of the operation with variable delay, corresponding to the code conversion time and reduction of the code conversion time itself in a cyclic mode to the minimum due to a reset signal at the beginning of the conversion, and in the address mode, reducing the maximum conversion time by half by introducing two formers, two elements OR, four elements And, the inverter and the corresponding links. The switch contains a channel counter, the counting input of which is connected to the clock generator output. The information inputs are connected to the input buses, and the outputs are connected via a decoder to a group of output buses and directly to the first inputs of the comparison unit, the second inputs of which are connected to the outputs of the pulse counter. , as well as a delay element and a trigger, the single output of which is connected to the trigger input of the high-frequency generator, characterized in that, in order to improve speed, two forms are introduced worlder, two elements OR, four AND elements and an inverter, whose input is connected to the output of the zero channel of the decoder and the first input of the first element AND, and the output is connected to the first input of the second AND element, the second input of which is connected to the output of the clock generator, the second input of the first element Both the first input of the first element .OR, the third input - with the third input of the first element AND, the first output of the comparison unit and the zero input of the trigger, and the output is connected to the first input of the second OR element, the second input of which through the first form The globalizer is connected to the output of the first element AND, the first output bus and the reset input of the pulse counter, and the output is connected to the ON / OFF input of the trigger, the zero output of which is connected to the second input of the first OR element, whose output through the second driver is connected to the input of the delay element whose output is connected with the second output bus, when the second and third outputs of the comparison unit are connected to the first inputs of the third and fourth elements, respectively, the second inputs of which are combined and connected to the output of high the frequency generator, the output of the third element I is connected to the third output bus and the subtracting input of the pulse counter, and the output of the fourth element I is connected to the fourth output bus and the summing input of the pulse counter. Sources of information taken into account in the examination 1. Dolgov V.A. and others. Commuting devices of automatic control systems. Energy, M., 1969, p. 70, fig. 47 2. Gitis E.I. Information converters for electronic digital computing devices. Energy, M., 1970, p. 234, fig. 5-10 b (prototype).