SG83719A1 - Method and system for buffering instructions in a processor - Google Patents

Method and system for buffering instructions in a processor

Info

Publication number
SG83719A1
SG83719A1 SG9902542A SG1999002542A SG83719A1 SG 83719 A1 SG83719 A1 SG 83719A1 SG 9902542 A SG9902542 A SG 9902542A SG 1999002542 A SG1999002542 A SG 1999002542A SG 83719 A1 SG83719 A1 SG 83719A1
Authority
SG
Singapore
Prior art keywords
processor
buffering instructions
buffering
instructions
Prior art date
Application number
SG9902542A
Other languages
English (en)
Inventor
Chandar G Subash
Deepak Mital
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/153,370 external-priority patent/US6275924B1/en
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of SG83719A1 publication Critical patent/SG83719A1/en

Links

SG9902542A 1998-05-21 1999-05-21 Method and system for buffering instructions in a processor SG83719A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IN1998MA1998 1998-05-21
US09/153,370 US6275924B1 (en) 1998-09-15 1998-09-15 System for buffering instructions in a processor by reissuing instruction fetches during decoder stall time

Publications (1)

Publication Number Publication Date
SG83719A1 true SG83719A1 (en) 2001-10-16

Family

ID=26324864

Family Applications (1)

Application Number Title Priority Date Filing Date
SG9902542A SG83719A1 (en) 1998-05-21 1999-05-21 Method and system for buffering instructions in a processor

Country Status (2)

Country Link
JP (1) JP3798180B2 (ja)
SG (1) SG83719A1 (ja)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0459232A2 (en) * 1990-05-29 1991-12-04 National Semiconductor Corporation Partially decoded instruction cache
US5101341A (en) * 1988-08-25 1992-03-31 Edgcore Technology, Inc. Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO
US5586295A (en) * 1993-01-21 1996-12-17 Advanced Micro Devices, Inc. Combination prefetch buffer and instruction cache

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5101341A (en) * 1988-08-25 1992-03-31 Edgcore Technology, Inc. Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO
EP0459232A2 (en) * 1990-05-29 1991-12-04 National Semiconductor Corporation Partially decoded instruction cache
US5586295A (en) * 1993-01-21 1996-12-17 Advanced Micro Devices, Inc. Combination prefetch buffer and instruction cache

Also Published As

Publication number Publication date
JP3798180B2 (ja) 2006-07-19
JP2000148479A (ja) 2000-05-30

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