SG44915A1 - Circuit arrangement comprising a plurality of sub-circuits and clock signal regeneration circuits - Google Patents

Circuit arrangement comprising a plurality of sub-circuits and clock signal regeneration circuits

Info

Publication number
SG44915A1
SG44915A1 SG1996009401A SG1996009401A SG44915A1 SG 44915 A1 SG44915 A1 SG 44915A1 SG 1996009401 A SG1996009401 A SG 1996009401A SG 1996009401 A SG1996009401 A SG 1996009401A SG 44915 A1 SG44915 A1 SG 44915A1
Authority
SG
Singapore
Prior art keywords
circuits
sub
clock signal
circuit arrangement
signal regeneration
Prior art date
Application number
SG1996009401A
Other languages
English (en)
Inventor
Petrus J A M Van De Wiel
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Publication of SG44915A1 publication Critical patent/SG44915A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Manipulation Of Pulses (AREA)
  • Multi Processors (AREA)
SG1996009401A 1991-12-09 1992-12-03 Circuit arrangement comprising a plurality of sub-circuits and clock signal regeneration circuits SG44915A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP91203207 1991-12-09

Publications (1)

Publication Number Publication Date
SG44915A1 true SG44915A1 (en) 1997-12-19

Family

ID=8208054

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1996009401A SG44915A1 (en) 1991-12-09 1992-12-03 Circuit arrangement comprising a plurality of sub-circuits and clock signal regeneration circuits

Country Status (6)

Country Link
US (1) US5448192A (US20100056889A1-20100304-C00004.png)
JP (1) JP3320469B2 (US20100056889A1-20100304-C00004.png)
KR (1) KR100291126B1 (US20100056889A1-20100304-C00004.png)
DE (1) DE69224971T2 (US20100056889A1-20100304-C00004.png)
SG (1) SG44915A1 (US20100056889A1-20100304-C00004.png)
TW (1) TW242204B (US20100056889A1-20100304-C00004.png)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5550499A (en) * 1995-04-18 1996-08-27 Cyrix Corporation Single delay line adjustable duty cycle clock generator
US5841305A (en) * 1997-03-20 1998-11-24 Cypress Semiconductor Corp. Circuit and method for adjusting duty cycles
US5969559A (en) * 1997-06-09 1999-10-19 Schwartz; David M. Method and apparatus for using a power grid for clock distribution in semiconductor integrated circuits
JPH11164335A (ja) * 1997-11-25 1999-06-18 Nec Corp マトリックススイッチ方法および装置
FR2871963B1 (fr) * 2004-06-22 2006-09-15 Thales Sa Dispositif electronique de generation de signaux de synchronisation
US7317343B1 (en) * 2005-10-25 2008-01-08 Lattice Semiconductor Corporation Pulse-generation circuit with multi-delay block and set-reset latches

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3760282A (en) * 1972-03-29 1973-09-18 Ibm Data recovery system
NL7315904A (nl) * 1973-11-21 1975-05-23 Philips Nv Inrichting voor omzetting van een analoog en een binair signaal.
US4021685A (en) * 1975-07-02 1977-05-03 Ferranti, Limited Pulse circuit for reshaping long line pulses
GB2120030B (en) * 1982-03-04 1986-11-12 Sansui Electric Co Digital signal demodulator circuit
US4514647A (en) * 1983-08-01 1985-04-30 At&T Bell Laboratories Chipset synchronization arrangement
NL8502234A (nl) * 1985-08-13 1987-03-02 Philips Nv Kloksignaalinrichting voor het regeneren van een kloksignaal.
US4801818A (en) * 1986-05-28 1989-01-31 Siemens Aktiengesellschaft Clock regeneration circuit
JPS63238714A (ja) * 1986-11-26 1988-10-04 Hitachi Ltd クロック供給システム
JPS63142719A (ja) * 1986-12-04 1988-06-15 Mitsubishi Electric Corp ３ステ−ト付相補型ｍｏｓ集積回路
US4761567A (en) * 1987-05-20 1988-08-02 Advanced Micro Devices, Inc. Clock scheme for VLSI systems
JPH07120225B2 (ja) * 1988-04-15 1995-12-20 富士通株式会社 半導体回路装置
US4870665A (en) * 1988-08-04 1989-09-26 Gte Government Systems Corporation Digital pulse generator having a programmable pulse width and a pulse repetition interval
JP2629028B2 (ja) * 1988-08-10 1997-07-09 株式会社日立製作所 クロック信号供給方法および装置
US4937468A (en) * 1989-01-09 1990-06-26 Sundstrand Corporation Isolation circuit for pulse waveforms
JP2756325B2 (ja) * 1989-12-07 1998-05-25 株式会社日立製作所 クロック供給回路
US5033067A (en) * 1989-12-15 1991-07-16 Alcatel Na Network Systems Corp. Variable shift register
US5225175A (en) * 1992-06-22 1993-07-06 Energy And Environmental Research Corporation Self-scrubbing removal of submicron particles from gaseous effluents

Also Published As

Publication number Publication date
JPH05257565A (ja) 1993-10-08
TW242204B (US20100056889A1-20100304-C00004.png) 1995-03-01
US5448192A (en) 1995-09-05
KR930013926A (ko) 1993-07-22
KR100291126B1 (ko) 2001-09-17
DE69224971T2 (de) 1998-10-15
JP3320469B2 (ja) 2002-09-03
DE69224971D1 (de) 1998-05-07

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