SG43012A1 - Cyclical redundancy check method and apparatus - Google Patents
Cyclical redundancy check method and apparatusInfo
- Publication number
- SG43012A1 SG43012A1 SG1996002233A SG1996002233A SG43012A1 SG 43012 A1 SG43012 A1 SG 43012A1 SG 1996002233 A SG1996002233 A SG 1996002233A SG 1996002233 A SG1996002233 A SG 1996002233A SG 43012 A1 SG43012 A1 SG 43012A1
- Authority
- SG
- Singapore
- Prior art keywords
- redundancy check
- check method
- cyclical redundancy
- crc
- dual
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M13/091—Parallel or block-wise CRC computation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1833—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Probability & Statistics with Applications (AREA)
- Quality & Reliability (AREA)
- General Physics & Mathematics (AREA)
- Signal Processing (AREA)
- Computer Security & Cryptography (AREA)
- Computing Systems (AREA)
- Error Detection And Correction (AREA)
- Detection And Correction Of Errors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/147,865 US5465260A (en) | 1993-11-04 | 1993-11-04 | Dual purpose cyclic redundancy check |
Publications (1)
Publication Number | Publication Date |
---|---|
SG43012A1 true SG43012A1 (en) | 1997-10-17 |
Family
ID=22523232
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG1996002233A SG43012A1 (en) | 1993-11-04 | 1994-10-18 | Cyclical redundancy check method and apparatus |
Country Status (6)
Country | Link |
---|---|
US (3) | US5465260A (de) |
EP (1) | EP0729674B1 (de) |
JP (1) | JPH09507118A (de) |
DE (1) | DE69429732D1 (de) |
SG (1) | SG43012A1 (de) |
WO (1) | WO1995012921A1 (de) |
Families Citing this family (77)
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US5629949A (en) * | 1993-09-21 | 1997-05-13 | Cirrus Logic, Inc. | Error correction verification method and apparatus using CRC check remainders |
US5602857A (en) * | 1993-09-21 | 1997-02-11 | Cirrus Logic, Inc. | Error correction method and apparatus |
US5473620A (en) * | 1993-09-21 | 1995-12-05 | Cirrus Logic, Inc. | Programmable redundancy/syndrome generator |
JPH09501788A (ja) * | 1994-03-09 | 1997-02-18 | フィリップス エレクトロニクス ネムローゼ フェンノートシャップ | 送受信装置、送受信方法、この送受信方法または送信装置により得られる記録担体 |
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EP0984451B1 (de) * | 1998-07-09 | 2005-12-14 | Hewlett-Packard Company, A Delaware Corporation | Verbessertes Datenschreiben auf Datenspeichermedium |
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US6438724B1 (en) * | 1999-03-16 | 2002-08-20 | International Business Machines Corporation | Method and apparatus for deterministically altering cyclic redundancy check information for data storage |
US6446234B1 (en) * | 1999-03-16 | 2002-09-03 | International Business Machines Corporation | Method and apparatus for updating cyclic redundancy check information for data storage |
US6915475B1 (en) | 1999-06-29 | 2005-07-05 | Emc Corporation | Data integrity management for data storage systems |
EP1065595A1 (de) * | 1999-06-30 | 2001-01-03 | Texas Instruments Incorporated | Erzeugung und Analyse von statistischen Daten |
US6662336B1 (en) | 1999-07-06 | 2003-12-09 | Cirrus Logic, Inc. | Error correction method and apparatus |
US6643818B1 (en) | 1999-11-19 | 2003-11-04 | International Business Machines Corporation | Storing and using the history of data transmission errors to assure data integrity |
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EP1146650A1 (de) * | 2000-04-10 | 2001-10-17 | Hewlett-Packard Company, A Delaware Corporation | Fehlerkorrektur für Datenauzeichnung und Übertragung |
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US7320101B1 (en) * | 2003-08-19 | 2008-01-15 | Altera Corporation | Fast parallel calculation of cyclic redundancy checks |
US7613991B1 (en) | 2003-08-19 | 2009-11-03 | Altera Corporation | Method and apparatus for concurrent calculation of cyclic redundancy checks |
US7353448B1 (en) | 2003-10-21 | 2008-04-01 | Marvell Semiconductor Israel Ltd. | Methods, architectures, circuits and systems for transmission error determination |
US7826614B1 (en) * | 2003-11-05 | 2010-11-02 | Globalfoundries Inc. | Methods and apparatus for passing initialization vector information from software to hardware to perform IPsec encryption operation |
US7472330B2 (en) * | 2003-11-26 | 2008-12-30 | Samsung Electronics Co., Ltd. | Magnetic memory which compares compressed fault maps |
US7426676B2 (en) * | 2004-01-14 | 2008-09-16 | Broadcom Corporation | Data retrieval from a storage device using a combined error correction and detection approach |
US7729427B2 (en) * | 2004-02-24 | 2010-06-01 | Intersil Americas Inc. | Pseudo-synchronous one wire bidirectional bus interface |
US7596699B2 (en) * | 2004-02-24 | 2009-09-29 | Intersil Americas Inc. | Battery authentication system |
US7434150B1 (en) | 2004-03-03 | 2008-10-07 | Marvell Israel (M.I.S.L.) Ltd. | Methods, circuits, architectures, software and systems for determining a data transmission error and/or checking or confirming such error determinations |
JP4260688B2 (ja) | 2004-06-09 | 2009-04-30 | 富士通株式会社 | データ送信装置、データ送受信システム、データ送信装置の制御方法およびデータ送受信システムの制御方法 |
US7398452B2 (en) * | 2004-12-16 | 2008-07-08 | Broadcom Corporation | Method and system for determining a signal quality metric in event of a CRC false positive |
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KR100690274B1 (ko) * | 2005-09-12 | 2007-03-09 | 삼성전자주식회사 | 다중 채널 직렬 통신을 위한 순환 중복 검사 장치 및 이를구비한 통신 시스템 |
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US8386878B2 (en) * | 2007-07-12 | 2013-02-26 | Samsung Electronics Co., Ltd. | Methods and apparatus to compute CRC for multiple code blocks |
US8555148B2 (en) * | 2007-09-18 | 2013-10-08 | Samsung Electronics Co., Ltd. | Methods and apparatus to generate multiple CRCs |
EP2096884A1 (de) | 2008-02-29 | 2009-09-02 | Koninklijke KPN N.V. | Telekommunikationsnetzwerk und Verfahren für den zeitbasierten Netzwerkzugang |
WO2009147735A1 (ja) * | 2008-06-04 | 2009-12-10 | 富士通株式会社 | 情報処理装置、データ送信装置およびデータ送信装置のデータ転送方法 |
WO2011080768A1 (en) * | 2009-12-29 | 2011-07-07 | Ferdinando Bedeschi | Memory devices comprising partitions with particular ecc attributes |
US8904115B2 (en) * | 2010-09-28 | 2014-12-02 | Texas Instruments Incorporated | Cache with multiple access pipelines |
US11392317B2 (en) | 2017-05-31 | 2022-07-19 | Fmad Engineering Kabushiki Gaisha | High speed data packet flow processing |
US10423358B1 (en) | 2017-05-31 | 2019-09-24 | FMAD Engineering GK | High-speed data packet capture and storage with playback capabilities |
US11128740B2 (en) * | 2017-05-31 | 2021-09-21 | Fmad Engineering Kabushiki Gaisha | High-speed data packet generator |
US11036438B2 (en) | 2017-05-31 | 2021-06-15 | Fmad Engineering Kabushiki Gaisha | Efficient storage architecture for high speed packet capture |
US10990326B2 (en) | 2017-05-31 | 2021-04-27 | Fmad Engineering Kabushiki Gaisha | High-speed replay of captured data packets |
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US4151510A (en) * | 1978-04-27 | 1979-04-24 | Honeywell Information Systems | Method and apparatus for an efficient error detection and correction system |
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JPS60230732A (ja) * | 1984-04-28 | 1985-11-16 | Nec Corp | 回線多重化crc符号生成装置 |
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JPS6332770A (ja) * | 1986-07-25 | 1988-02-12 | Matsushita Electric Ind Co Ltd | 磁気記録再生装置 |
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JP2695195B2 (ja) * | 1988-09-02 | 1997-12-24 | 三菱電機株式会社 | 誤り訂正回路 |
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US5422895A (en) * | 1992-01-09 | 1995-06-06 | Quantum Corporation | Cross-checking for on-the-fly Reed Solomon error correction code |
US5375127A (en) * | 1992-03-25 | 1994-12-20 | Ncr Corporation | Method and apparatus for generating Reed-Soloman error correcting code across multiple word boundaries |
US5379305A (en) * | 1992-07-20 | 1995-01-03 | Digital Equipment Corporation | Error correction system with selectable error correction capabilities |
US5444719A (en) * | 1993-01-26 | 1995-08-22 | International Business Machines Corporation | Adjustable error-correction composite Reed-Solomon encoder/syndrome generator |
-
1993
- 1993-11-04 US US08/147,865 patent/US5465260A/en not_active Expired - Lifetime
-
1994
- 1994-10-18 SG SG1996002233A patent/SG43012A1/en unknown
- 1994-10-18 JP JP7513259A patent/JPH09507118A/ja active Pending
- 1994-10-18 DE DE69429732T patent/DE69429732D1/de not_active Expired - Lifetime
- 1994-10-18 US US08/325,717 patent/US5671237A/en not_active Expired - Lifetime
- 1994-10-18 WO PCT/US1994/012138 patent/WO1995012921A1/en active IP Right Grant
- 1994-10-18 EP EP95900404A patent/EP0729674B1/de not_active Expired - Lifetime
-
1996
- 1996-10-02 US US08/725,320 patent/US5724368A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0729674A4 (de) | 1997-10-15 |
US5671237A (en) | 1997-09-23 |
US5465260A (en) | 1995-11-07 |
US5724368A (en) | 1998-03-03 |
EP0729674B1 (de) | 2002-01-23 |
WO1995012921A1 (en) | 1995-05-11 |
JPH09507118A (ja) | 1997-07-15 |
EP0729674A1 (de) | 1996-09-04 |
DE69429732D1 (de) | 2002-03-14 |
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