SG11201906818RA - Interconnect structure for electrical connecting a pair of microwave transmission lines formed on a pair of spaced structure members - Google Patents

Interconnect structure for electrical connecting a pair of microwave transmission lines formed on a pair of spaced structure members

Info

Publication number
SG11201906818RA
SG11201906818RA SG11201906818RA SG11201906818RA SG11201906818RA SG 11201906818R A SG11201906818R A SG 11201906818RA SG 11201906818R A SG11201906818R A SG 11201906818RA SG 11201906818R A SG11201906818R A SG 11201906818RA SG 11201906818R A SG11201906818R A SG 11201906818RA
Authority
SG
Singapore
Prior art keywords
pair
international
microwave transmission
applicant
interconnect structure
Prior art date
Application number
SG11201906818RA
Inventor
Susan Trulli
Christopher Laighton
Elicia Harper
Original Assignee
Raytheon Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Raytheon Co filed Critical Raytheon Co
Publication of SG11201906818RA publication Critical patent/SG11201906818RA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P1/00—Auxiliary devices
    • H01P1/04—Fixed joints
    • H01P1/047—Strip line joints
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P11/00—Apparatus or processes specially adapted for manufacturing waveguides or resonators, lines, or other devices of the waveguide type
    • H01P11/001—Manufacturing waveguides or transmission lines of the waveguide type
    • H01P11/003—Manufacturing lines with conductors on a substrate, e.g. strip lines, slot lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P3/00—Waveguides; Transmission lines of the waveguide type
    • H01P3/02—Waveguides; Transmission lines of the waveguide type with two longitudinal conductors
    • H01P3/026—Coplanar striplines [CPS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P3/00—Waveguides; Transmission lines of the waveguide type
    • H01P3/02—Waveguides; Transmission lines of the waveguide type with two longitudinal conductors
    • H01P3/08—Microstrips; Strip lines
    • H01P3/081—Microstriplines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P5/00—Coupling devices of the waveguide type
    • H01P5/02—Coupling devices of the waveguide type with invariable factor of coupling
    • H01P5/022—Transitions between lines of the same kind and shape, but with different dimensions
    • H01P5/028—Transitions between lines of the same kind and shape, but with different dimensions between strip lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
    • H01L2223/6633—Transition between different waveguide types
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6683—High-frequency adaptations for monolithic microwave integrated circuit [MMIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401—Structure
    • H01L2224/24011—Deposited, e.g. MCM-D type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24155—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H01L2224/82102—Forming a build-up interconnect by additive methods, e.g. direct writing using jetting, e.g. ink jet
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H01L2224/82104—Forming a build-up interconnect by additive methods, e.g. direct writing using screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00015—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Structure Of Printed Boards (AREA)
  • Waveguide Connection Structure (AREA)
  • Combinations Of Printed Boards (AREA)
  • Developing Agents For Electrophotography (AREA)

Abstract

INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 02 August 2018 (02.08.2018) WIP0 I PCT omit VIII °nolo olomoimilmuno oimIE (10) International Publication Number WO 2018/140345 Al (51) International Patent Classification: H01P 5/02 (2006.01) HO1L 23/00 (2006.01) HO1P 11/00 (2006.01) H01L 23/66 (2006.01) H05K 1/14 (2006.01) HO1P 1/04 (2006.01) (21) International Application Number: PCT/US2018/014653 (22) International Filing Date: 22 January 2018 (22.01.2018) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 15/415,367 25 January 2017 (25.01.2017) US (71) Applicant: RAYTHEON COMPANY [US/US]; 870 Winter Street, Waltham, MA 02451-1449 (US). (72) Inventors: TRULLI, Susan, C.; 52 Middle Street, Lexing- ton, MA 02421 (US). LAIGHTON, Christopher, M.; 397 Sargent Road, Boxborough, MA 01719 (US). HARPER, Elicia, K.; 34 Tremont Street, Unit 4, Chelsea, MA 02150 (US). (74) Agent: MOFFORD, Donald, F. et al.; Daly, Crowley, Mofford & Durkee, LLP, 354A Turnpike St., Suite 301A, Canton, MA 02021 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, (54) Title: INTERCONNECT STRUCTURE FOR ELECTRICAL CONNECTING A PAIR OF MICROWAVE TRANSMISSION = LINES FORMED ON A PAIR OF SPACED STRUCTURE MEMBERS 75a 10 FIG. 10A O 00 O C (57) : A structure having pair of structure members separated by a gap and an interconnect structure member disposed in the gap. The interconnect structure member includes: a fill-structure having opposing sides in direct contact with the opposing sides of the first structure member and the second structure member; and, an interconnecting microwave transmission line disposed on the fill- structure electrically interconnecting the microwave transmission line of the first structure member to the second member structure. An electrically conductive member is disposed over a signal line of, and electrically connected to the ground conductor the interconnecting microwave transmission. [Continued on next page] WO 2018/140345 Al MIDEDIMOMOIDEIREEMOMMHOIIMOMODEVOIMIE SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: as to applicant's entitlement to apply for and be granted a patent (Rule 4.17(11)) as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) Published: — with international search report (Art. 21(3))
SG11201906818RA 2017-01-25 2018-01-22 Interconnect structure for electrical connecting a pair of microwave transmission lines formed on a pair of spaced structure members SG11201906818RA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/415,367 US9978698B1 (en) 2017-01-25 2017-01-25 Interconnect structure for electrical connecting a pair of microwave transmission lines formed on a pair of spaced structure members
PCT/US2018/014653 WO2018140345A1 (en) 2017-01-25 2018-01-22 Interconnect structure for electrical connecting a pair of microwave transmission lines formed on a pair of spaced structure members

Publications (1)

Publication Number Publication Date
SG11201906818RA true SG11201906818RA (en) 2019-08-27

Family

ID=61257096

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201906818RA SG11201906818RA (en) 2017-01-25 2018-01-22 Interconnect structure for electrical connecting a pair of microwave transmission lines formed on a pair of spaced structure members

Country Status (6)

Country Link
US (1) US9978698B1 (en)
EP (1) EP3574548B1 (en)
JP (1) JP7023287B2 (en)
KR (1) KR102314975B1 (en)
SG (1) SG11201906818RA (en)
WO (1) WO2018140345A1 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10785863B2 (en) * 2018-04-09 2020-09-22 Raytheon Company Circuit support and cooling structure
US11894322B2 (en) 2018-05-29 2024-02-06 Analog Devices, Inc. Launch structures for radio frequency integrated device packages
EP3850662B1 (en) 2018-09-14 2023-05-17 Raytheon Company Module base with integrated thermal spreader and heat sink for thermal and structural management of high-performance integrated circuits or other devices
US11417615B2 (en) * 2018-11-27 2022-08-16 Analog Devices, Inc. Transition circuitry for integrated circuit die
TWI733331B (en) * 2020-02-11 2021-07-11 華邦電子股份有限公司 Semiconductor device and method of manufacturing the same
US11032947B1 (en) 2020-02-17 2021-06-08 Raytheon Company Tailored coldplate geometries for forming multiple coefficient of thermal expansion (CTE) zones
US11309267B2 (en) 2020-07-15 2022-04-19 Winbond Electronics Corp. Semiconductor device including uneven contact in passivation layer and method of manufacturing the same
US11744021B2 (en) 2022-01-21 2023-08-29 Analog Devices, Inc. Electronic assembly

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04223703A (en) * 1990-12-26 1992-08-13 Tdk Corp High frequency transmission line
JP3399771B2 (en) * 1997-02-25 2003-04-21 三菱電機株式会社 Microwave circuit
JP4551541B2 (en) 2000-08-10 2010-09-29 新日本無線株式会社 Gunn diode oscillator
EP1180918B1 (en) * 2000-08-16 2010-01-27 Ericsson AB Method for dispensing adhesive on a circuit-board carrier member and circuit-board provided thereby
US6949992B2 (en) * 2002-03-20 2005-09-27 Powerwave Technologies, Inc. System and method of providing highly isolated radio frequency interconnections
JP3916072B2 (en) * 2003-02-04 2007-05-16 住友電気工業株式会社 AC coupling circuit
JP4897451B2 (en) * 2006-12-04 2012-03-14 ルネサスエレクトロニクス株式会社 Semiconductor device
US7978030B2 (en) * 2007-02-12 2011-07-12 Finisar Corporation High-speed interconnects
JP2008227720A (en) 2007-03-09 2008-09-25 Anritsu Corp Transmission line connection structure
US8760342B2 (en) * 2009-03-31 2014-06-24 Kyocera Corporation Circuit board, high frequency module, and radar apparatus
JP2011061585A (en) 2009-09-11 2011-03-24 Asahi Kasei Electronics Co Ltd High frequency device
US8937382B2 (en) * 2011-06-27 2015-01-20 Intel Corporation Secondary device integration into coreless microelectronic device packages
JP2016178361A (en) 2015-03-18 2016-10-06 株式会社東芝 antenna

Also Published As

Publication number Publication date
US9978698B1 (en) 2018-05-22
KR102314975B1 (en) 2021-10-19
JP7023287B2 (en) 2022-02-21
KR20190108610A (en) 2019-09-24
EP3574548B1 (en) 2023-10-11
JP2020505851A (en) 2020-02-20
EP3574548A1 (en) 2019-12-04
WO2018140345A1 (en) 2018-08-02

Similar Documents

Publication Publication Date Title
SG11201906818RA (en) Interconnect structure for electrical connecting a pair of microwave transmission lines formed on a pair of spaced structure members
SG11201900511VA (en) Electromagnetic sensing and detection of ingestible event markers
SG11201909160WA (en) Multispecific polypeptide constructs having constrained cd3 binding and methods of using the same
SG11201810364VA (en) Electronic mortgage brokering and monitoring
SG11201811184UA (en) Lag -3 binding members
SG11201900611QA (en) Electrical connector
SG11201810979SA (en) Systems and methods for switching driving mode of vehicle
SG11201910129SA (en) Redundant controls for negative pressure wound therapy systems
SG11201811608TA (en) Systems and methods for transportation service safety assessment
SG11201906366RA (en) Camera module and mobile terminal
SG11202000330XA (en) Concept for generating an enhanced sound field description or a modified sound field description using a multi-point sound field description
SG11201906782WA (en) Selectors for nozzles and memory elements
SG11201807002TA (en) Intention signaling for an autonomous vehicle
SG11201806709PA (en) Universal tokenisation system for blockchain-based cryptocurrencies
SG11201804506RA (en) Systems and methods for rendering multiple levels of detail
SG11202000285QA (en) Concept for generating an enhanced sound-field description or a modified sound field description using a multi-layer description
SG11201806553WA (en) Device and arrangement for controlling an electromagnetic wave, methods of forming and operating the same
SG11201906657QA (en) Systems and methods for modulated image capture
SG11201810887UA (en) Baff-r targeted chimeric antigen receptor-modified t-cells and uses thereof
SG11201906159XA (en) Socket side thermal system
SG11201908042TA (en) Smartcard
SG11201808046VA (en) System for wireless power transfer
SG11201803998PA (en) Systems and methods for updating sequence of services
SG11201910206QA (en) Methods and compositions for treating inflammatory gastrointestinal disorders
SG11201907309YA (en) Devices and methods for requesting and/or supplying information