SG11201900966TA - Semiconductor devices employing field effect transistors (fets) with multiple channel structures without shallow trench isolation (sti) void-induced electrical shorts - Google Patents

Semiconductor devices employing field effect transistors (fets) with multiple channel structures without shallow trench isolation (sti) void-induced electrical shorts

Info

Publication number
SG11201900966TA
SG11201900966TA SG11201900966TA SG11201900966TA SG11201900966TA SG 11201900966T A SG11201900966T A SG 11201900966TA SG 11201900966T A SG11201900966T A SG 11201900966TA SG 11201900966T A SG11201900966T A SG 11201900966TA SG 11201900966T A SG11201900966T A SG 11201900966TA
Authority
SG
Singapore
Prior art keywords
international
sti
void
channel structures
san diego
Prior art date
Application number
SG11201900966TA
Inventor
Jeffrey Xu
Haining Yang
Jun Yuan
Kern Rim
Periannan Chidambaram
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of SG11201900966TA publication Critical patent/SG11201900966TA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Nanotechnology (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)

Abstract

1) 316(1), 318— 310(2),__ `320(2) 312(1), 314 12(2). 314 0 308(1) 308(2) 304 312(3), 306(3) 314316(3), 322(1) 306(2) 322(2) 318 306(1) 310(3) 316(4), 318 312(4), 314 310(4) 302(2) FIG. 3 302(1) 306(4) ') 306(5) 306(6) (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 22 March 2018 (22.03.2018) omit n OH E 100111111011001101101101110#011 (10) International Publication Number WO 2018/053090 Al WIPO I PCT (51) International Patent Classification: H01L 21/762 (2006.01) H01L 29/06 (2006.01) (21) International Application Number: PCT/US2017/051505 (22) International Filing Date: 14 September 2017 (14.09.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 15/266,214 15 September 2016 (15.09.2016) US (71) Applicant: QUALCOMM INCORPORATED [US/US]; Attn: International IP Administration, 5775 Morehouse Dri- ve, San Diego, California 92121-1714 (US). (72) Inventors: XU, Jeffrey, Junhao; 5775 Morehouse Dri- ve, San Diego, California 92121 (US). YANG, Haining; 5775 Morehouse Drive, San Diego, California 92121 (US). YUAN, Jun; 5775 Morehouse Drive, San Diego, Cali- fornia 92121 (US). RIM, Kern; 5775 Morehouse Drive, San Diego, California 92121 (US). CHIDAMBARAM, Pe- riannan; 5775 Morehouse Drive, San Diego, California 92121 (US). (74) Agent: TERRANOVA, Steven, N.; Withrow & Terrano- va, PLLC, 106 Pinedale Springs Way, Cary, North Carolina 27511 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, (54) Title: SEMICONDUCTOR DEVICES EMPLOYING FIELD EFFECT TRANSISTORS (FETS) WITH MULTIPLE CHANNEL STRUCTURES WITHOUT SHALLOW TRENCH ISOLATION (STI) VOID-INDUCED ELECTRICAL SHORTS (57) : Semiconductor devices employing Field Effect Transistors (FETs) with multiple channel structures without shallow trench isolation (STI) void-induced electrical shorts are disclosed. In one aspect, a semiconductor device is provided that includes a substrate. The semiconductor device includes channel structures disposed over the substrate, the channel structures corresponding to a FET. An STI trench is formed between each corresponding pair of channel structures. Each STI trench includes a bottom region filled with a lower quality oxide, and a top region filled with a higher quality oxide. The lower quality oxide is susceptible to void formation in the bottom region during particular fabrication steps of the semiconductor device. However, the higher quality oxide is not susceptible to void formation. Thus, the higher quality oxide does not include voids with which a gate may electrically couple to [Continued on next page] WO 2018/053090 Al MIDEDIMOMOIDEIREEMOOMMILIMMOMMEHOIS KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: as to applicant's entitlement to apply for and be granted a patent (Rule 4.17(ii)) as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) Published: — with international search report (Art. 21(3)) other active components, thus preventing STI void-induced electrical shorts in the semiconductor device.
SG11201900966TA 2016-09-15 2017-09-14 Semiconductor devices employing field effect transistors (fets) with multiple channel structures without shallow trench isolation (sti) void-induced electrical shorts SG11201900966TA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/266,214 US10141305B2 (en) 2016-09-15 2016-09-15 Semiconductor devices employing field effect transistors (FETs) with multiple channel structures without shallow trench isolation (STI) void-induced electrical shorts
PCT/US2017/051505 WO2018053090A1 (en) 2016-09-15 2017-09-14 Semiconductor devices employing field effect transistors (fets) with multiple channel structures without shallow trench isolation (sti) void-induced electrical shorts

Publications (1)

Publication Number Publication Date
SG11201900966TA true SG11201900966TA (en) 2019-04-29

Family

ID=60043280

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201900966TA SG11201900966TA (en) 2016-09-15 2017-09-14 Semiconductor devices employing field effect transistors (fets) with multiple channel structures without shallow trench isolation (sti) void-induced electrical shorts

Country Status (8)

Country Link
US (1) US10141305B2 (en)
EP (1) EP3513429B1 (en)
KR (1) KR20190046859A (en)
CN (1) CN109844929B (en)
AU (1) AU2017325703B2 (en)
SG (1) SG11201900966TA (en)
TW (1) TWI670766B (en)
WO (1) WO2018053090A1 (en)

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7033945B2 (en) 2004-06-01 2006-04-25 Applied Materials Gap filling with a composite layer
KR100713924B1 (en) * 2005-12-23 2007-05-07 주식회사 하이닉스반도체 Fin transistor and method for forming thereof
KR100803576B1 (en) * 2006-06-14 2008-02-15 주식회사 인피트론 A composition for transplant comprising adipose stem cells and adipocytes
US8138102B2 (en) * 2008-08-21 2012-03-20 International Business Machines Corporation Method of placing a semiconducting nanostructure and semiconductor device including the semiconducting nanostructure
KR101471858B1 (en) * 2008-09-05 2014-12-12 삼성전자주식회사 Semiconductor device having bar type active pattern and method of manufacturing the same
JP5841306B2 (en) * 2009-05-08 2016-01-13 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
KR20110024629A (en) 2009-09-02 2011-03-09 주식회사 하이닉스반도체 Method for fabricating isolation in semiconductor device
US8653608B2 (en) * 2009-10-27 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET design with reduced current crowding
US8466027B2 (en) 2011-09-08 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Silicide formation and associated devices
US8445356B1 (en) * 2012-01-05 2013-05-21 International Business Machines Corporation Integrated circuit having back gating, improved isolation and reduced well resistance and method to fabricate same
US9589803B2 (en) 2012-08-10 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Gate electrode of field effect transistor
US9123771B2 (en) 2013-02-13 2015-09-01 Globalfoundries Inc. Shallow trench isolation integration methods and devices formed thereby
US8895446B2 (en) 2013-02-18 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Fin deformation modulation
US9087870B2 (en) 2013-05-29 2015-07-21 GlobalFoundries, Inc. Integrated circuits including FINFET devices with shallow trench isolation that includes a thermal oxide layer and methods for making the same
US8975155B2 (en) * 2013-07-10 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a shallow trench isolation structure
EP2947693B1 (en) 2014-05-22 2022-07-13 IMEC vzw Method of Producing a III-V Fin Structure
US9508719B2 (en) * 2014-11-26 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field effect transistor (FinFET) device with controlled end-to-end critical dimension and method for forming the same

Also Published As

Publication number Publication date
US20180076197A1 (en) 2018-03-15
US10141305B2 (en) 2018-11-27
TWI670766B (en) 2019-09-01
CN109844929A (en) 2019-06-04
BR112019004476A2 (en) 2019-05-28
CN109844929B (en) 2023-11-10
AU2017325703A1 (en) 2019-02-28
KR20190046859A (en) 2019-05-07
EP3513429A1 (en) 2019-07-24
AU2017325703B2 (en) 2022-09-01
TW201824384A (en) 2018-07-01
EP3513429B1 (en) 2023-08-02
WO2018053090A1 (en) 2018-03-22

Similar Documents

Publication Publication Date Title
SG11201804506RA (en) Systems and methods for rendering multiple levels of detail
SG11201807205XA (en) Quality of service (qos) management in wireless networks
SG11201901373YA (en) Electronic power devices integrated with an engineered substrate
SG11201805152UA (en) Superconducting bump bonds
SG11201909040PA (en) Mobility between areas with heterogeneous network slices
SG11201907118WA (en) Write data path to reduce charge leakage of negative boost
SG11201809123UA (en) Informing base station regarding user equipment's reception of beam change instruction
SG11201408364VA (en) Coding sei nal units for video coding
SG11201903090SA (en) High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency
SG11201900340QA (en) Land grid based multi size pad package
SG11201908818YA (en) Partial band configuration for channel state information
SG11201408118YA (en) Video parameter set for hevc and extensions
SG11201807206SA (en) Connectivity to a local area network via a cellular radio access technology
SG11201900269XA (en) Channel sensing for independent links
SG11201901196RA (en) Wafer-level package with enhanced performance
SG11201906546TA (en) Narrowband time-division duplex frame structure for narrowband communications
SG11201901858QA (en) Techniques for contending for access to a radio frequency spectrum band using a coordinated listen before talk procedure
SG11201804600YA (en) Methods and apparatus for selecting enhanced distributed channel access parameters for different stations
SG11201902525VA (en) Techniques for adjusting transmit power in wireless communications
SG11201903613VA (en) User plane model for non-3gpp access to fifth generation core network
SG11201900218TA (en) Layer 2 relay to support coverage and resource-constrained devices in wireless networks
SG11201907928UA (en) Spatial-division multiple access (sdma) across multiple operators
SG11201900969SA (en) Access stratum security for efficient packet processing
SG11201908688PA (en) Techniques and apparatuses for channel state information feedback performance for introduction of 64-qam in machine type communication devices
SG11201902202PA (en) Method and apparatus for reestablishing radio communication links due to radio link failure