SG11201810291PA - High speed voltage level shifter - Google Patents

High speed voltage level shifter

Info

Publication number
SG11201810291PA
SG11201810291PA SG11201810291PA SG11201810291PA SG11201810291PA SG 11201810291P A SG11201810291P A SG 11201810291PA SG 11201810291P A SG11201810291P A SG 11201810291PA SG 11201810291P A SG11201810291P A SG 11201810291PA SG 11201810291P A SG11201810291P A SG 11201810291PA
Authority
SG
Singapore
Prior art keywords
california
international
input
san diego
morehouse
Prior art date
Application number
SG11201810291PA
Inventor
Venkat Narayanan
Rakesh Vattikonda
de Lu
Ramaprasath Vilangudipitchai
Samrat Sinharoy
Rui Chen
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of SG11201810291PA publication Critical patent/SG11201810291PA/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/35613—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356182—Bistable circuits using complementary field-effect transistors with additional means for controlling the main nodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)

Abstract

INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property 111111101111 0 1110101011111 011101 0 0111111111111111111111111111111111111110111111 Organization International Bureau (10) International Publication Number (43) International Publication Date ...... WO 2018/005085 Al 04 January 2018 (04.01.2018) WIP0 I PCT (51) (21) (22) (25) Filing Language: (26) (30) (71) Applicant: QUALCOMM INCORPORATED [US/US]; (72) International Patent Classification: ye, San Diego, California 92121-1714 (US). VILAN- H03K 3/012 (2006.01) H03K 3/356 (2006.01) GUDIPITCHAI, Ramaprasath; 5775 Morehouse Drive, International Application Number: San Diego, California 92121-1714 (US). SINHAROY, PCT/US2017/037335 Samrat; 5775 Morehouse Drive, San Diego, California 92121-1714 (US). CHEN, Rui; 5775 Morehouse Drive, International Filing Date: San Diego, California 92121-1714 (US). 13 June 2017 (13.06.2017) (74) Agent: WORLEY, Eugene; Loza & Loza, LLP, 305 North English Second Avenue #127, Upland, California 91786 (US). Publication Language: English (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, Priority Data: AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, 62/357,164 30 June 2016 (30.06.2016) US CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, 15/367,706 02 December 2016 (02.12.2016) US DZ, EC, EE, EG, ES, FL GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, ATTN: International IP Administration, 5775 Morehouse KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, Drive, San Diego, California 92121-1714 (US). MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, Inventors: NARAYANAN, Venkat; 5775 Morehouse Dri- SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, ye, San Diego, California 92121-1714 (US). VATTIKON-TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. DA, Rakesh; 5775 Morehouse Drive, San Diego, Cali- fornia 92121-1714 (US). LU, De; 5775 Morehouse Dri- - = put (54) Title: HIGH SPEED VOLTAGE LEVEL SHIFTER 252-- DN -250 -- 220 FIG. 2 gate (250) having to receive includes a second a second input (225) configured to receive the enable signal in the second the first NOR gate, and an output (Z_N) coupled to the third input of the by a supply voltage of the second power domain. 210 — 255 = = • 257 227- = = _ ENB D = = = = 225 -, = = 222 ZN a first input (252) configured to receive a first input signal an enable signal (ENB) in a second power domain, a third NOR gate (220) having a first input (222) configured to : A voltage level shifter includes a first NOR in a first power domain, a second input (255) configured (257), and an output (Z). The voltage level shifter also a second input signal (D) in the first power domain, domain, a third input (227) coupled to the output of NOR gate. The first and second NOR gates are powered 1-1 kr) GC c:::: ) (57) In (D_N) C:::: ) m • 0 ---- receive GC power 1-1 © first ei O [Continued on next page] WO 2018/005085 Al MIDEDIMOMOIDEIREEMOMIIMINIRMOMEHOIMIE (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: — as to applicant's entitlement to apply for and be granted a patent (Rule 4.17(ii)) — as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) Published: — with international search report (Art. 21(3))
SG11201810291PA 2016-06-30 2017-06-13 High speed voltage level shifter SG11201810291PA (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201662357164P 2016-06-30 2016-06-30
US15/367,706 US9859893B1 (en) 2016-06-30 2016-12-02 High speed voltage level shifter
PCT/US2017/037335 WO2018005085A1 (en) 2016-06-30 2017-06-13 High speed voltage level shifter

Publications (1)

Publication Number Publication Date
SG11201810291PA true SG11201810291PA (en) 2019-01-30

Family

ID=59216033

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201810291PA SG11201810291PA (en) 2016-06-30 2017-06-13 High speed voltage level shifter

Country Status (9)

Country Link
US (1) US9859893B1 (en)
EP (1) EP3479479B1 (en)
JP (1) JP6657430B2 (en)
KR (1) KR101987881B1 (en)
CN (1) CN109417382B (en)
BR (1) BR112018076655B1 (en)
ES (1) ES2899949T3 (en)
SG (1) SG11201810291PA (en)
WO (1) WO2018005085A1 (en)

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US9948303B2 (en) 2016-06-30 2018-04-17 Qualcomm Incorporated High speed voltage level shifter
US11145378B2 (en) * 2019-02-19 2021-10-12 Texas Instruments Incorporated Methods and apparatus to improve performance while reading a one-time programmable memory
CN110545098B (en) * 2019-10-08 2022-11-29 重庆百瑞互联电子技术有限公司 CMOS level converter, operation method, device and equipment
WO2021220479A1 (en) 2020-04-30 2021-11-04 株式会社ソシオネクスト Input circuit
CN115189689A (en) * 2021-06-02 2022-10-14 台湾积体电路制造股份有限公司 Multi-bit level shifter and method of operating the same
KR102578556B1 (en) 2021-09-15 2023-09-14 주식회사 에이티지랩 Method for evaluating athletic ability of children with developmental disabilities based gamification
KR102507813B1 (en) 2021-11-26 2023-03-08 동국대학교 산학협력단 Method and system for evaluating athletic ability of children with developmental disabilities

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Also Published As

Publication number Publication date
JP6657430B2 (en) 2020-03-04
US20180006650A1 (en) 2018-01-04
US9859893B1 (en) 2018-01-02
EP3479479B1 (en) 2021-11-17
CN109417382B (en) 2023-01-03
WO2018005085A1 (en) 2018-01-04
BR112018076655A2 (en) 2019-03-26
BR112018076655B1 (en) 2023-10-03
ES2899949T3 (en) 2022-03-15
EP3479479A1 (en) 2019-05-08
KR20190003813A (en) 2019-01-09
JP2019522934A (en) 2019-08-15
CN109417382A (en) 2019-03-01
KR101987881B1 (en) 2019-06-11

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